From 067b01c5e61b9fd8654668c6388f9119bb179760 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 9 Jul 2020 11:07:02 +0200 Subject: [PATCH] radv: add radv_pipeline_generate_vgt_gs_out() Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_pipeline.c | 55 ++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9e43e73d10b..d7a05c03e2a 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4602,12 +4602,40 @@ gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs, S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi)); } +static void +radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs, + struct radv_pipeline *pipeline, + const VkGraphicsPipelineCreateInfo *pCreateInfo, + const struct radv_graphics_pipeline_create_info *extra) +{ + uint32_t gs_out; + + if (radv_pipeline_has_gs(pipeline)) { + gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); + } else if (radv_pipeline_has_tess(pipeline)) { + if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) { + gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST; + } else { + gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode); + } + } else { + gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology); + } + + if (extra && extra->use_rectlist) { + gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP; + if (radv_pipeline_has_ngg(pipeline)) + gs_out = V_028A6C_VGT_OUT_RECT_V0; + } + + radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out); +} + static void radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo, const struct radv_graphics_pipeline_create_info *extra, - const struct radv_blend_state *blend, - unsigned gs_out) + const struct radv_blend_state *blend) { struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs; struct radeon_cmdbuf *cs = &pipeline->cs; @@ -4636,12 +4664,11 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend); radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline); radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo); + radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, pCreateInfo, extra); if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline)) gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline); - radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out); - pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4); assert(ctx_cs->cdw <= ctx_cs->max_dw); @@ -4803,24 +4830,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline, pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo); - uint32_t gs_out; - - if (radv_pipeline_has_gs(pipeline)) { - gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); - } else if (radv_pipeline_has_tess(pipeline)) { - if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) - gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST; - else - gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode); - } else { - gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology); - } - if (extra && extra->use_rectlist) { - gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP; - if (radv_pipeline_has_ngg(pipeline)) - gs_out = V_028A6C_VGT_OUT_RECT_V0; - } - radv_pipeline_init_input_assembly_state(pipeline, pCreateInfo, extra); radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra); @@ -4902,7 +4911,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline); result = radv_pipeline_scratch_init(device, pipeline); - radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, gs_out); + radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend); return result; } -- 2.30.2