From 068617f0948b411fcf9cdf047c6dfc600a0689bb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Jul 2019 16:12:57 -0700 Subject: [PATCH] Pack hi and lo registers separately --- passes/pmgen/ice40_dsp.cc | 47 +++++++++++++++++------------ passes/pmgen/ice40_dsp.pmg | 62 ++++++++++++++++++++++++++------------ 2 files changed, 70 insertions(+), 39 deletions(-) diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index d4e2914d9..6b6fd5640 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -34,13 +34,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm) #if 1 log("\n"); - log("ffA: %s\n", log_id(st.ffA, "--")); - log("ffB: %s\n", log_id(st.ffB, "--")); - log("mul: %s\n", log_id(st.mul, "--")); - log("ffH: %s\n", log_id(st.ffH, "--")); - log("addAB: %s\n", log_id(st.addAB, "--")); - log("muxAB: %s\n", log_id(st.muxAB, "--")); - log("ffO: %s\n", log_id(st.ffO, "--")); + log("ffA: %s\n", log_id(st.ffA, "--")); + log("ffB: %s\n", log_id(st.ffB, "--")); + log("mul: %s\n", log_id(st.mul, "--")); + log("ffH: %s\n", log_id(st.ffH, "--")); + log("addAB: %s\n", log_id(st.addAB, "--")); + log("muxAB: %s\n", log_id(st.muxAB, "--")); + log("ffO_lo: %s\n", log_id(st.ffO_lo, "--")); + log("ffO_hi: %s\n", log_id(st.ffO_hi, "--")); #endif log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul)); @@ -133,8 +134,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm) if (st.ffH) log(" ffH:%s", log_id(st.ffH)); - if (st.ffO) - log(" ffO:%s", log_id(st.ffO)); + if (st.ffO_lo) + log(" ffO_lo:%s", log_id(st.ffO_lo)); + if (st.ffO_hi) + log(" ffO_hi:%s", log_id(st.ffO_hi)); log("\n"); } @@ -158,20 +161,22 @@ void create_ice40_dsp(ice40_dsp_pm &pm) // SB_MAC16 Output Interface - SigSpec O = st.ffO ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH); - if (GetSize(O) < 32) - O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); + SigSpec O_lo = (st.ffO_lo ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(0,16); + if (GetSize(O_lo) < 16) + O_lo.append(pm.module->addWire(NEW_ID, 16-GetSize(O_lo))); + SigSpec O_hi = (st.ffO_hi ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(16,16); + if (GetSize(O_hi) < 16) + O_hi.append(pm.module->addWire(NEW_ID, 16-GetSize(O_hi))); + SigSpec O{O_hi,O_lo}; cell->setPort("\\O", O); - // MAC only if ffO exists and adder's other input (sigO) - // is output of ffO bool accum = false; if (st.addAB) { if (st.addA) - accum = (st.ffO && st.addAB->getPort("\\B") == st.ffO->getPort("\\Q")); + accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == O); else if (st.addB) - accum = (st.ffO && st.addAB->getPort("\\A") == st.ffO->getPort("\\Q")); + accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == O); else log_abort(); if (accum) log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); @@ -209,12 +214,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffH ? State::S1 : State::S0); cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0); - cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2)); + cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO_hi ? 1 : (st.addAB ? 0 : 3), 2)); cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2)); cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1); cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2)); - cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2)); + cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO_lo ? 1 : (st.addAB ? 0 : 3), 2)); cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2)); cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1); cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2)); @@ -226,8 +231,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm) pm.autoremove(st.mul); pm.autoremove(st.ffH); pm.autoremove(st.addAB); - if (st.ffO) - st.ffO->connections_.at("\\Q").replace(st.sigO, pm.module->addWire(NEW_ID, GetSize(st.sigO))); + if (st.ffO_lo) + st.ffO_lo->connections_.at("\\Q").replace(O.extract(0,16), pm.module->addWire(NEW_ID, 16)); + if (st.ffO_hi) + st.ffO_hi->connections_.at("\\Q").replace(O.extract(16,16), pm.module->addWire(NEW_ID, 16)); } struct Ice40DspPass : public Pass { diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index a74bd7902..0684edc1b 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -60,11 +60,13 @@ match ffH optional endmatch -code sigH clock clock_pol +code sigH sigO clock clock_pol sigH = port(mul, \Y); + sigO = sigH; if (ffH) { sigH = port(ffH, \Q); + sigO = sigH; SigBit c = port(ffH, \CLK).as_bit(); bool cp = param(ffH, \CLK_POLARITY).as_bool(); @@ -95,12 +97,10 @@ endmatch code addAB sigO sigO_signed if (addA) { addAB = addA; - sigO = port(addAB, \B); sigO_signed = param(addAB, \B_SIGNED).as_bool(); } if (addB) { addAB = addB; - sigO = port(addAB, \A); sigO_signed = param(addAB, \A_SIGNED).as_bool(); } if (addAB) { @@ -112,6 +112,8 @@ code addAB sigO sigO_signed reject; if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool())) reject; + + sigO = port(addAB, \Y); } endcode @@ -132,36 +134,58 @@ match muxB optional endmatch -code muxAB +code muxAB sigO muxAB = addAB; if (muxA) muxAB = muxA; if (muxB) muxAB = muxB; + if (muxA || muxB) + sigO = port(muxAB, \Y); endcode -match ffO - if muxAB - select ffO->type.in($dff) - filter nusers(port(muxAB, \Y)) == 2 - filter includes(port(ffO, \D).to_sigbit_set(), port(muxAB, \Y).to_sigbit_set()) +match ffO_lo + select ffO_lo->type.in($dff) + filter nusers(sigO.extract(0,16)) == 2 + filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,16).to_sigbit_set()) + optional +endmatch + +match ffO_hi + select ffO_hi->type.in($dff) + filter nusers(sigO.extract(16,16)) == 2 + filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,16).to_sigbit_set()) optional endmatch code clock clock_pol sigO - if (ffO) { - SigBit c = port(ffO, \CLK).as_bit(); - bool cp = param(ffO, \CLK_POLARITY).as_bool(); + if (ffO_lo || ffO_hi) { + if (ffO_lo) { + SigBit c = port(ffO_lo, \CLK).as_bit(); + bool cp = param(ffO_lo, \CLK_POLARITY).as_bool(); - if (port(ffO, \Q) != sigO) { - sigO = port(muxAB, \Y); - sigO.replace(port(ffO, \D), port(ffO, \Q)); + if (clock != SigBit() && (c != clock || cp != clock_pol)) + reject; + + clock = c; + clock_pol = cp; + + if (port(ffO_lo, \Q) != sigO.extract(0,16)) + sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q)); } - if (clock != SigBit() && (c != clock || cp != clock_pol)) - reject; + if (ffO_hi) { + SigBit c = port(ffO_hi, \CLK).as_bit(); + bool cp = param(ffO_hi, \CLK_POLARITY).as_bool(); - clock = c; - clock_pol = cp; + if (clock != SigBit() && (c != clock || cp != clock_pol)) + reject; + + clock = c; + clock_pol = cp; + + if (port(ffO_hi, \Q) != sigO.extract(16,16)) + sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q)); + } } endcode -- 2.30.2