From 068d44188ee1ec044d54b9aaac55c0187b274176 Mon Sep 17 00:00:00 2001
From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 21 Mar 2021 17:53:21 -0300
Subject: [PATCH] Revert removal of *.value from Enums

---
 src/soc/simple/issuer.py | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 9a95f8d5..9ca922e5 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -82,25 +82,25 @@ def get_predint(m, mask):
     invert = Signal()
     unary = Signal()
     with m.Switch(mask):
-        with m.Case(SVP64PredInt.ALWAYS):
+        with m.Case(SVP64PredInt.ALWAYS.value):
             comb += regread.eq(0)
             comb += invert.eq(1)
-        with m.Case(SVP64PredInt.R3_UNARY):
+        with m.Case(SVP64PredInt.R3_UNARY.value):
             comb += regread.eq(3)
             comb += unary.eq(1)
-        with m.Case(SVP64PredInt.R3):
+        with m.Case(SVP64PredInt.R3.value):
             comb += regread.eq(3)
-        with m.Case(SVP64PredInt.R3_N):
+        with m.Case(SVP64PredInt.R3_N.value):
             comb += regread.eq(3)
             comb += invert.eq(1)
-        with m.Case(SVP64PredInt.R10):
+        with m.Case(SVP64PredInt.R10.value):
             comb += regread.eq(10)
-        with m.Case(SVP64PredInt.R10_N):
+        with m.Case(SVP64PredInt.R10_N.value):
             comb += regread.eq(10)
             comb += invert.eq(1)
-        with m.Case(SVP64PredInt.R30):
+        with m.Case(SVP64PredInt.R30.value):
             comb += regread.eq(30)
-        with m.Case(SVP64PredInt.R30_N):
+        with m.Case(SVP64PredInt.R30_N.value):
             comb += regread.eq(30)
             comb += invert.eq(1)
     return regread, invert, unary
@@ -113,28 +113,28 @@ def get_predcr(m, mask):
     idx = Signal(2)
     invert = Signal()
     with m.Switch(mask):
-        with m.Case(SVP64PredCR.LT):
+        with m.Case(SVP64PredCR.LT.value):
             comb += idx.eq(0)
             comb += invert.eq(1)
-        with m.Case(SVP64PredCR.GE):
+        with m.Case(SVP64PredCR.GE.value):
             comb += idx.eq(0)
             comb += invert.eq(0)
-        with m.Case(SVP64PredCR.GT):
+        with m.Case(SVP64PredCR.GT.value):
             comb += idx.eq(1)
             comb += invert.eq(1)
-        with m.Case(SVP64PredCR.LE):
+        with m.Case(SVP64PredCR.LE.value):
             comb += idx.eq(1)
             comb += invert.eq(0)
-        with m.Case(SVP64PredCR.EQ):
+        with m.Case(SVP64PredCR.EQ.value):
             comb += idx.eq(2)
             comb += invert.eq(1)
-        with m.Case(SVP64PredCR.NE):
+        with m.Case(SVP64PredCR.NE.value):
             comb += idx.eq(1)
             comb += invert.eq(0)
-        with m.Case(SVP64PredCR.SO):
+        with m.Case(SVP64PredCR.SO.value):
             comb += idx.eq(3)
             comb += invert.eq(1)
-        with m.Case(SVP64PredCR.NS):
+        with m.Case(SVP64PredCR.NS.value):
             comb += idx.eq(3)
             comb += invert.eq(0)
     return idx, invert
-- 
2.30.2