From 06ba0585d67cf607a5141d5bfcd4a6a67607ae70 Mon Sep 17 00:00:00 2001
From: Alexander Ivchenko <alexander.ivchenko@intel.com>
Date: Tue, 14 Oct 2014 08:19:17 +0000
Subject: [PATCH] AVX-512. 60/n. Update 128bit ashrv insn pattern.

gcc/
	* config/i386/sse.md
	(define_mode_iterator VI128_128 [V16QI V8HI V2DI]): Delete.
	(define_expand "vashr<mode>3<mask_name>"): Add masking,
	use VI12_128 mode iterator.
	(define_expand "ashrv2di3<mask_name>"): New.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216178
---
 gcc/ChangeLog          | 15 +++++++++++++++
 gcc/config/i386/sse.md | 40 +++++++++++++++++++++++++++++-----------
 2 files changed, 44 insertions(+), 11 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5ee1d70950e..18cefaf2a89 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2014-10-14  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+	    Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Ilya Tocar  <ilya.tocar@intel.com>
+	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
+	    Ilya Verbin  <ilya.verbin@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* config/i386/sse.md
+	(define_mode_iterator VI128_128 [V16QI V8HI V2DI]): Delete.
+	(define_expand "vashr<mode>3<mask_name>"): Add masking,
+	use VI12_128 mode iterator.
+	(define_expand "ashrv2di3<mask_name>"): New.
+
 2014-10-14  Alexander Ivchenko  <alexander.ivchenko@intel.com>
 	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 	    Anna Tikhonova  <anna.tikhonova@intel.com>
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 99fd5cf75ff..f4586d94da9 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -503,7 +503,6 @@
 (define_mode_iterator VI12_128 [V16QI V8HI])
 (define_mode_iterator VI14_128 [V16QI V4SI])
 (define_mode_iterator VI124_128 [V16QI V8HI V4SI])
-(define_mode_iterator VI128_128 [V16QI V8HI V2DI])
 (define_mode_iterator VI24_128 [V8HI V4SI])
 (define_mode_iterator VI248_128 [V8HI V4SI V2DI])
 (define_mode_iterator VI48_128 [V4SI V2DI])
@@ -15529,17 +15528,36 @@
 	  (match_operand:VI48_256 2 "nonimmediate_operand")))]
   "TARGET_AVX2")
 
-(define_expand "vashr<mode>3"
-  [(set (match_operand:VI128_128 0 "register_operand")
-	(ashiftrt:VI128_128
-	  (match_operand:VI128_128 1 "register_operand")
-	  (match_operand:VI128_128 2 "nonimmediate_operand")))]
-  "TARGET_XOP"
+(define_expand "vashr<mode>3<mask_name>"
+  [(set (match_operand:VI12_128 0 "register_operand")
+	(ashiftrt:VI12_128
+	  (match_operand:VI12_128 1 "register_operand")
+	  (match_operand:VI12_128 2 "nonimmediate_operand")))]
+  "TARGET_XOP || (TARGET_AVX512BW && TARGET_AVX512VL)"
 {
-  rtx neg = gen_reg_rtx (<MODE>mode);
-  emit_insn (gen_neg<mode>2 (neg, operands[2]));
-  emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], neg));
-  DONE;
+  if (TARGET_XOP)
+    {
+      rtx neg = gen_reg_rtx (<MODE>mode);
+      emit_insn (gen_neg<mode>2 (neg, operands[2]));
+      emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], neg));
+      DONE;
+    }
+})
+
+(define_expand "vashrv2di3<mask_name>"
+  [(set (match_operand:V2DI 0 "register_operand")
+	(ashiftrt:V2DI
+	  (match_operand:V2DI 1 "register_operand")
+	  (match_operand:V2DI 2 "nonimmediate_operand")))]
+  "TARGET_XOP || TARGET_AVX512VL"
+{
+  if (TARGET_XOP)
+    {
+      rtx neg = gen_reg_rtx (V2DImode);
+      emit_insn (gen_negv2di2 (neg, operands[2]));
+      emit_insn (gen_xop_shav2di3 (operands[0], operands[1], neg));
+      DONE;
+    }
 })
 
 (define_expand "vashrv4si3"
-- 
2.30.2