From 06bc9e41f4da836809323409de0a27892cba655a Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Fri, 27 Dec 2013 14:03:55 +0000 Subject: [PATCH] i386.c (ix86_print_operand): Print EVEX's RC modifiers. * config/i386/i386.c (ix86_print_operand): Print EVEX's RC modifiers. * config/i386/i386.md (define_constants): Define EVEx's RC constants. * gcc/config/i386/sse.md (3): Extend to support EVEX's rounding control. (*3): Ditto. (mul3): Ditto. (*mul3): Ditto. (_div3): Ditto. (_sqrt2): Ditto. (fma_fmadd_): Ditto. (avx512f_fmadd__mask): Ditto. (avx512f_fmadd__mask3): Ditto. (fma_fmsub_): Ditto. (avx512f_fmsub__mask): Ditto. (avx512f_fmsub__mask3): Ditto. (fma_fnmadd_): Ditto. (avx512f_fnmadd__mask): Ditto. (avx512f_fnmadd__mask3): Ditto. (fma_fnmsub_): Ditto. (avx512f_fnmsub__mask): Ditto. (avx512f_fnmsub__mask3): Ditto. (fma_fmaddsub_): Ditto. (avx512f_fmaddsub__mask): Ditto. (avx512f_fmaddsub__mask3): Ditto. (fma_fmsubadd_): Ditto. (avx512f_fmsubadd__mask): Ditto. (avx512f_fmsubadd__mask3): Ditto. (fmai_vmfmadd_): Ditto. (*fmai_fmadd_): Ditto. (*fmai_fmsub_): Ditto. (*fmai_fnmadd_): Ditto. (*fmai_fnmsub_): Ditto. (sse_cvtsi2ss): Ditto. (sse_cvtsi2ssq): Ditto. (sse_cvtss2si): Ditto. (sse_cvtss2siq): Ditto. (cvtusi232): Ditto. (cvtusi264): Ditto. (float2): Ditto. (ufloatv16siv16sf2): Ditto. (avx512f_fix_notruncv16sfv16si): Ditto. (avx512f_ufix_notruncv16sfv16si): Ditto. (sse2_cvtsi2sdq): Ditto. (avx512f_vcvtss2usi): Ditto. (avx512f_vcvtss2usiq): Ditto. (avx512f_vcvtsd2usi): Ditto. (avx512f_vcvtsd2usiq): Ditto. (sse2_cvtsd2si): Ditto. (sse2_cvtsd2siq): Ditto. (avx512f_cvtpd2dq512): Ditto. (avx512f_ufix_notruncv8dfv8si): Ditto. (avx512f_cvtpd2ps512): Ditto. (avx512f_scalef): Ditto. (3): Ditto. (*avx2_3): Ditto. (avx512er_exp2avx512er_rcp28): Ditto. (avx512er_rsqrt28): Ditto. (avx512f_fmadd__maskz): New. * config/i386/subst.md (SUBST_A): New. (round_name): Ditto. (round_mask_operand2): Ditto. (round_mask_operand3): Ditto. (round_mask_scalar_operand3): Ditto. (round_sd_mask_operand4): Ditto. (round_op2): Ditto. (round_op3): Ditto. (round_op4): Ditto. (round_op5): Ditto. (round_op6): Ditto. (round_mask_op2): Ditto. (round_mask_op3): Ditto. (round_mask_scalar_op3): Ditto. (round_sd_mask_op4): Ditto. (round_constraint): Ditto. (round_constraint2): Ditto. (round_constraint3): Ditto. (round_nimm_predicate): Ditto. (round_mode512bit_condition): Ditto. (round_modev4sf_condition): Ditto. (round_codefor): Ditto. (round_opnum): Ditto. (round): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin Co-Authored-By: Sergey Lega From-SVN: r206220 --- gcc/ChangeLog | 94 ++++++++ gcc/config/i386/i386.c | 32 +++ gcc/config/i386/i386.md | 10 + gcc/config/i386/sse.md | 480 ++++++++++++++++++++------------------- gcc/config/i386/subst.md | 42 ++++ 5 files changed, 425 insertions(+), 233 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d8c272afb26..afc4cc13862 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,97 @@ +2013-12-27 Alexander Ivchenko + Maxim Kuznetsov + Sergey Lega + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/i386.c (ix86_print_operand): Print EVEX's RC modifiers. + * config/i386/i386.md (define_constants): Define EVEx's RC constants. + * gcc/config/i386/sse.md (3): Extend + to support EVEX's rounding control. + (*3): Ditto. + (mul3): Ditto. + (*mul3): Ditto. + (_div3): Ditto. + (_sqrt2): Ditto. + (fma_fmadd_): Ditto. + (avx512f_fmadd__mask): Ditto. + (avx512f_fmadd__mask3): Ditto. + (fma_fmsub_): Ditto. + (avx512f_fmsub__mask): Ditto. + (avx512f_fmsub__mask3): Ditto. + (fma_fnmadd_): Ditto. + (avx512f_fnmadd__mask): Ditto. + (avx512f_fnmadd__mask3): Ditto. + (fma_fnmsub_): Ditto. + (avx512f_fnmsub__mask): Ditto. + (avx512f_fnmsub__mask3): Ditto. + (fma_fmaddsub_): Ditto. + (avx512f_fmaddsub__mask): Ditto. + (avx512f_fmaddsub__mask3): Ditto. + (fma_fmsubadd_): Ditto. + (avx512f_fmsubadd__mask): Ditto. + (avx512f_fmsubadd__mask3): Ditto. + (fmai_vmfmadd_): Ditto. + (*fmai_fmadd_): Ditto. + (*fmai_fmsub_): Ditto. + (*fmai_fnmadd_): Ditto. + (*fmai_fnmsub_): Ditto. + (sse_cvtsi2ss): Ditto. + (sse_cvtsi2ssq): Ditto. + (sse_cvtss2si): Ditto. + (sse_cvtss2siq): Ditto. + (cvtusi232): Ditto. + (cvtusi264): Ditto. + (float2): Ditto. + (ufloatv16siv16sf2): Ditto. + (avx512f_fix_notruncv16sfv16si): Ditto. + (avx512f_ufix_notruncv16sfv16si): Ditto. + (sse2_cvtsi2sdq): Ditto. + (avx512f_vcvtss2usi): Ditto. + (avx512f_vcvtss2usiq): Ditto. + (avx512f_vcvtsd2usi): Ditto. + (avx512f_vcvtsd2usiq): Ditto. + (sse2_cvtsd2si): Ditto. + (sse2_cvtsd2siq): Ditto. + (avx512f_cvtpd2dq512): Ditto. + (avx512f_ufix_notruncv8dfv8si): Ditto. + (avx512f_cvtpd2ps512): Ditto. + (avx512f_scalef): Ditto. + (3): Ditto. + (*avx2_3): Ditto. + (avx512er_exp2avx512er_rcp28): Ditto. + (avx512er_rsqrt28): Ditto. + (avx512f_fmadd__maskz): New. + * config/i386/subst.md (SUBST_A): New. + (round_name): Ditto. + (round_mask_operand2): Ditto. + (round_mask_operand3): Ditto. + (round_mask_scalar_operand3): Ditto. + (round_sd_mask_operand4): Ditto. + (round_op2): Ditto. + (round_op3): Ditto. + (round_op4): Ditto. + (round_op5): Ditto. + (round_op6): Ditto. + (round_mask_op2): Ditto. + (round_mask_op3): Ditto. + (round_mask_scalar_op3): Ditto. + (round_sd_mask_op4): Ditto. + (round_constraint): Ditto. + (round_constraint2): Ditto. + (round_constraint3): Ditto. + (round_nimm_predicate): Ditto. + (round_mode512bit_condition): Ditto. + (round_modev4sf_condition): Ditto. + (round_codefor): Ditto. + (round_opnum): Ditto. + (round): Ditto. + 2013-12-26 H.J. Lu PR target/59588 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 0cf0a9da0a2..2fc9b802993 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -14990,6 +14990,38 @@ ix86_print_operand (FILE *file, rtx x, int code) fputs ("{z}", file); return; + case 'R': + gcc_assert (CONST_INT_P (x)); + + if (ASSEMBLER_DIALECT == ASM_INTEL) + fputs (", ", file); + + switch (INTVAL (x)) + { + case ROUND_NEAREST_INT: + fputs ("{rn-sae}", file); + break; + case ROUND_NEG_INF: + fputs ("{rd-sae}", file); + break; + case ROUND_POS_INF: + fputs ("{ru-sae}", file); + break; + case ROUND_ZERO: + fputs ("{rz-sae}", file); + break; + case ROUND_SAE: + fputs ("{sae}", file); + break; + default: + gcc_unreachable (); + } + + if (ASSEMBLER_DIALECT == ASM_ATT) + fputs (", ", file); + + return; + case '*': if (ASSEMBLER_DIALECT == ASM_ATT) putc ('*', file); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 7a16c8ec1df..c7ed099f38a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -241,6 +241,16 @@ (ROUND_NO_EXC 0x8) ]) +;; Constants to represent AVX512F embeded rounding +(define_constants + [(ROUND_NEAREST_INT 0) + (ROUND_NEG_INF 1) + (ROUND_POS_INF 2) + (ROUND_ZERO 3) + (NO_ROUND 4) + (ROUND_SAE 5) + ]) + ;; Constants to represent pcomtrue/pcomfalse variants (define_constants [(PCOM_FALSE 0) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 2cbbb14ccea..4c9f310594e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1272,23 +1272,23 @@ } [(set_attr "isa" "noavx,noavx,avx,avx")]) -(define_expand "3" +(define_expand "3" [(set (match_operand:VF 0 "register_operand") (plusminus:VF - (match_operand:VF 1 "nonimmediate_operand") - (match_operand:VF 2 "nonimmediate_operand")))] - "TARGET_SSE && " + (match_operand:VF 1 "") + (match_operand:VF 2 "")))] + "TARGET_SSE && && " "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*3" +(define_insn "*3" [(set (match_operand:VF 0 "register_operand" "=x,v") (plusminus:VF - (match_operand:VF 1 "nonimmediate_operand" "0,v") - (match_operand:VF 2 "nonimmediate_operand" "xm,vm")))] - "TARGET_SSE && ix86_binary_operator_ok (, mode, operands) && " + (match_operand:VF 1 "" "0,v") + (match_operand:VF 2 "" "xm,")))] + "TARGET_SSE && ix86_binary_operator_ok (, mode, operands) && && " "@ \t{%2, %0|%0, %2} - v\t{%2, %1, %0|%0, %1, %2}" + v\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseadd") (set_attr "prefix" "") @@ -1311,23 +1311,23 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) -(define_expand "mul3" +(define_expand "mul3" [(set (match_operand:VF 0 "register_operand") (mult:VF - (match_operand:VF 1 "nonimmediate_operand") - (match_operand:VF 2 "nonimmediate_operand")))] - "TARGET_SSE && " + (match_operand:VF 1 "") + (match_operand:VF 2 "")))] + "TARGET_SSE && && " "ix86_fixup_binary_operands_no_copy (MULT, mode, operands);") -(define_insn "*mul3" +(define_insn "*mul3" [(set (match_operand:VF 0 "register_operand" "=x,v") (mult:VF - (match_operand:VF 1 "nonimmediate_operand" "%0,v") - (match_operand:VF 2 "nonimmediate_operand" "xm,vm")))] - "TARGET_SSE && ix86_binary_operator_ok (MULT, mode, operands) && " + (match_operand:VF 1 "" "%0,v") + (match_operand:VF 2 "" "xm,")))] + "TARGET_SSE && ix86_binary_operator_ok (MULT, mode, operands) && && " "@ mul\t{%2, %0|%0, %2} - vmul\t{%2, %1, %0|%0, %1, %2}" + vmul\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "ssemul") (set_attr "prefix" "") @@ -1378,15 +1378,15 @@ } }) -(define_insn "_div3" +(define_insn "_div3" [(set (match_operand:VF 0 "register_operand" "=x,v") (div:VF (match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "nonimmediate_operand" "xm,vm")))] - "TARGET_SSE && " + (match_operand:VF 2 "" "xm,")))] + "TARGET_SSE && && " "@ div\t{%2, %0|%0, %2} - vdiv\t{%2, %1, %0|%0, %1, %2}" + vdiv\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "ssediv") (set_attr "prefix" "") @@ -1470,11 +1470,11 @@ } }) -(define_insn "_sqrt2" +(define_insn "_sqrt2" [(set (match_operand:VF 0 "register_operand" "=v") - (sqrt:VF (match_operand:VF 1 "nonimmediate_operand" "vm")))] - "TARGET_SSE && " - "%vsqrt\t{%1, %0|%0, %1}" + (sqrt:VF (match_operand:VF 1 "" "")))] + "TARGET_SSE && && " + "%vsqrt\t{%1, %0|%0, %1}" [(set_attr "type" "sse") (set_attr "atom_sse_attr" "sqrt") (set_attr "btver2_sse_attr" "sqrt") @@ -2741,210 +2741,224 @@ (match_operand:FMAMODE 3 "nonimmediate_operand")))] "") -(define_insn "fma_fmadd_" +(define_expand "avx512f_fmadd__maskz" + [(match_operand:VF_512 0 "register_operand") + (match_operand:VF_512 1 "nonimmediate_operand") + (match_operand:VF_512 2 "nonimmediate_operand") + (match_operand:VF_512 3 "nonimmediate_operand") + (match_operand: 4 "register_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_fma_fmadd__maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "fma_fmadd_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE - (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x") - (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") - (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x")))] - "" - "@ - vfmadd132\t{%2, %3, %0|%0, %3, %2} - vfmadd213\t{%3, %2, %0|%0, %2, %3} - vfmadd231\t{%2, %1, %0|%0, %1, %2} + (match_operand:FMAMODE 1 "" "%0,0,v,x,x") + (match_operand:FMAMODE 2 "" ",v,,x,m") + (match_operand:FMAMODE 3 "" "v,,0,xm,x")))] + " && " + "@ + vfmadd132\t{%2, %3, %0|%0, %3, %2} + vfmadd213\t{%3, %2, %0|%0, %2, %3} + vfmadd231\t{%2, %1, %0|%0, %1, %2} vfmadd\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fmadd__mask" +(define_insn "avx512f_fmadd__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 (fma:VF_512 (match_operand:VF_512 1 "register_operand" "0,0") - (match_operand:VF_512 2 "nonimmediate_operand" "vm,v") - (match_operand:VF_512 3 "nonimmediate_operand" "v,vm")) + (match_operand:VF_512 2 "" ",v") + (match_operand:VF_512 3 "" "v,")) (match_dup 1) (match_operand: 4 "register_operand" "k,k")))] "TARGET_AVX512F" "@ - vfmadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} - vfmadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" + vfmadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} + vfmadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fmadd__mask3" +(define_insn "avx512f_fmadd__mask3" [(set (match_operand:VF_512 0 "register_operand" "=x") (vec_merge:VF_512 (fma:VF_512 (match_operand:VF_512 1 "register_operand" "x") - (match_operand:VF_512 2 "nonimmediate_operand" "vm") + (match_operand:VF_512 2 "" "") (match_operand:VF_512 3 "register_operand" "0")) (match_dup 3) (match_operand: 4 "register_operand" "k")))] "TARGET_AVX512F" - "vfmadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" + "vfmadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "isa" "fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "fma_fmsub_" +(define_insn "fma_fmsub_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE - (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x") - (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") + (match_operand:FMAMODE 1 "" "%0, 0, v, x,x") + (match_operand:FMAMODE 2 "" ",v,,x,m") (neg:FMAMODE - (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x"))))] - "" + (match_operand:FMAMODE 3 "" "v,,0,xm,x"))))] + " && " "@ - vfmsub132\t{%2, %3, %0|%0, %3, %2} - vfmsub213\t{%3, %2, %0|%0, %2, %3} - vfmsub231\t{%2, %1, %0|%0, %1, %2} + vfmsub132\t{%2, %3, %0|%0, %3, %2} + vfmsub213\t{%3, %2, %0|%0, %2, %3} + vfmsub231\t{%2, %1, %0|%0, %1, %2} vfmsub\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fmsub__mask" +(define_insn "avx512f_fmsub__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 (fma:VF_512 (match_operand:VF_512 1 "register_operand" "0,0") - (match_operand:VF_512 2 "nonimmediate_operand" "vm,v") + (match_operand:VF_512 2 "" ",v") (neg:VF_512 - (match_operand:VF_512 3 "nonimmediate_operand" "v,vm"))) + (match_operand:VF_512 3 "" "v,"))) (match_dup 1) (match_operand: 4 "register_operand" "k,k")))] "TARGET_AVX512F" "@ - vfmsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} - vfmsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" + vfmsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} + vfmsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fmsub__mask3" +(define_insn "avx512f_fmsub__mask3" [(set (match_operand:VF_512 0 "register_operand" "=v") (vec_merge:VF_512 (fma:VF_512 (match_operand:VF_512 1 "register_operand" "v") - (match_operand:VF_512 2 "nonimmediate_operand" "vm") + (match_operand:VF_512 2 "" "") (neg:VF_512 (match_operand:VF_512 3 "register_operand" "0"))) (match_dup 3) (match_operand: 4 "register_operand" "k")))] "TARGET_AVX512F" - "vfmsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" + "vfmsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "isa" "fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "fma_fnmadd_" +(define_insn "fma_fnmadd_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (neg:FMAMODE - (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x")) - (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") - (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x")))] - "" - "@ - vfnmadd132\t{%2, %3, %0|%0, %3, %2} - vfnmadd213\t{%3, %2, %0|%0, %2, %3} - vfnmadd231\t{%2, %1, %0|%0, %1, %2} + (match_operand:FMAMODE 1 "" "%0,0,v,x,x")) + (match_operand:FMAMODE 2 "" ",v,,x,m") + (match_operand:FMAMODE 3 "" "v,,0,xm,x")))] + " && " + "@ + vfnmadd132\t{%2, %3, %0|%0, %3, %2} + vfnmadd213\t{%3, %2, %0|%0, %2, %3} + vfnmadd231\t{%2, %1, %0|%0, %1, %2} vfnmadd\t{%3, %2, %1, %0|%0, %1, %2, %3} vfnmadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fnmadd__mask" +(define_insn "avx512f_fnmadd__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 (fma:VF_512 (neg:VF_512 (match_operand:VF_512 1 "register_operand" "0,0")) - (match_operand:VF_512 2 "nonimmediate_operand" "vm,v") - (match_operand:VF_512 3 "nonimmediate_operand" "v,vm")) + (match_operand:VF_512 2 "" ",v") + (match_operand:VF_512 3 "" "v,")) (match_dup 1) (match_operand: 4 "register_operand" "k,k")))] "TARGET_AVX512F" "@ - vfnmadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} - vfnmadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" + vfnmadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} + vfnmadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fnmadd__mask3" +(define_insn "avx512f_fnmadd__mask3" [(set (match_operand:VF_512 0 "register_operand" "=v") (vec_merge:VF_512 (fma:VF_512 (neg:VF_512 (match_operand:VF_512 1 "register_operand" "v")) - (match_operand:VF_512 2 "nonimmediate_operand" "vm") + (match_operand:VF_512 2 "" "") (match_operand:VF_512 3 "register_operand" "0")) (match_dup 3) (match_operand: 4 "register_operand" "k")))] "TARGET_AVX512F" - "vfnmadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" + "vfnmadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "isa" "fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "fma_fnmsub_" +(define_insn "fma_fnmsub_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (neg:FMAMODE - (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x")) - (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") + (match_operand:FMAMODE 1 "" "%0,0,v,x,x")) + (match_operand:FMAMODE 2 "" ",v,,x,m") (neg:FMAMODE - (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x"))))] - "" + (match_operand:FMAMODE 3 "" "v,,0,xm,x"))))] + " && " "@ - vfnmsub132\t{%2, %3, %0|%0, %3, %2} - vfnmsub213\t{%3, %2, %0|%0, %2, %3} - vfnmsub231\t{%2, %1, %0|%0, %1, %2} + vfnmsub132\t{%2, %3, %0|%0, %3, %2} + vfnmsub213\t{%3, %2, %0|%0, %2, %3} + vfnmsub231\t{%2, %1, %0|%0, %1, %2} vfnmsub\t{%3, %2, %1, %0|%0, %1, %2, %3} vfnmsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fnmsub__mask" +(define_insn "avx512f_fnmsub__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 (fma:VF_512 (neg:VF_512 (match_operand:VF_512 1 "register_operand" "0,0")) - (match_operand:VF_512 2 "nonimmediate_operand" "vm,v") + (match_operand:VF_512 2 "" ",v") (neg:VF_512 - (match_operand:VF_512 3 "nonimmediate_operand" "v,vm"))) + (match_operand:VF_512 3 "" "v,"))) (match_dup 1) (match_operand: 4 "register_operand" "k,k")))] "TARGET_AVX512F" "@ - vfnmsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} - vfnmsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" + vfnmsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} + vfnmsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fnmsub__mask3" +(define_insn "avx512f_fnmsub__mask3" [(set (match_operand:VF_512 0 "register_operand" "=v") (vec_merge:VF_512 (fma:VF_512 (neg:VF_512 (match_operand:VF_512 1 "register_operand" "v")) - (match_operand:VF_512 2 "nonimmediate_operand" "vm") + (match_operand:VF_512 2 "" "") (neg:VF_512 (match_operand:VF_512 3 "register_operand" "0"))) (match_dup 3) (match_operand: 4 "register_operand" "k")))] "TARGET_AVX512F" - "vfnmsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" + "vfnmsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "isa" "fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) @@ -2983,109 +2997,109 @@ DONE; }) -(define_insn "fma_fmaddsub_" +(define_insn "fma_fmaddsub_" [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") (unspec:VF - [(match_operand:VF 1 "nonimmediate_operand" "%0, 0, v, x,x") - (match_operand:VF 2 "nonimmediate_operand" "vm, v,vm, x,m") - (match_operand:VF 3 "nonimmediate_operand" " v,vm, 0,xm,x")] + [(match_operand:VF 1 "" "%0,0,v,x,x") + (match_operand:VF 2 "" ",v,,x,m") + (match_operand:VF 3 "" "v,,0,xm,x")] UNSPEC_FMADDSUB))] - "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && " + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && && " "@ - vfmaddsub132\t{%2, %3, %0|%0, %3, %2} - vfmaddsub213\t{%3, %2, %0|%0, %2, %3} - vfmaddsub231\t{%2, %1, %0|%0, %1, %2} + vfmaddsub132\t{%2, %3, %0|%0, %3, %2} + vfmaddsub213\t{%3, %2, %0|%0, %2, %3} + vfmaddsub231\t{%2, %1, %0|%0, %1, %2} vfmaddsub\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmaddsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fmaddsub__mask" +(define_insn "avx512f_fmaddsub__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "0,0") - (match_operand:VF_512 2 "nonimmediate_operand" "vm,v") - (match_operand:VF_512 3 "nonimmediate_operand" "v,vm")] + (match_operand:VF_512 2 "" ",v") + (match_operand:VF_512 3 "" "v,")] UNSPEC_FMADDSUB) (match_dup 1) (match_operand: 4 "register_operand" "k,k")))] "TARGET_AVX512F" "@ - vfmaddsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} - vfmaddsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" + vfmaddsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} + vfmaddsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fmaddsub__mask3" +(define_insn "avx512f_fmaddsub__mask3" [(set (match_operand:VF_512 0 "register_operand" "=v") (vec_merge:VF_512 (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "v") - (match_operand:VF_512 2 "nonimmediate_operand" "vm") + (match_operand:VF_512 2 "" "") (match_operand:VF_512 3 "register_operand" "0")] UNSPEC_FMADDSUB) (match_dup 3) (match_operand: 4 "register_operand" "k")))] "TARGET_AVX512F" - "vfmaddsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" + "vfmaddsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "isa" "fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "fma_fmsubadd_" +(define_insn "fma_fmsubadd_" [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") (unspec:VF - [(match_operand:VF 1 "nonimmediate_operand" "%0, 0, v, x,x") - (match_operand:VF 2 "nonimmediate_operand" "vm, v,vm, x,m") + [(match_operand:VF 1 "" "%0,0,v,x,x") + (match_operand:VF 2 "" ",v,,x,m") (neg:VF - (match_operand:VF 3 "nonimmediate_operand" " v,vm, 0,xm,x"))] + (match_operand:VF 3 "" "v,,0,xm,x"))] UNSPEC_FMADDSUB))] - "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && " + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && && " "@ - vfmsubadd132\t{%2, %3, %0|%0, %3, %2} - vfmsubadd213\t{%3, %2, %0|%0, %2, %3} - vfmsubadd231\t{%2, %1, %0|%0, %1, %2} + vfmsubadd132\t{%2, %3, %0|%0, %3, %2} + vfmsubadd213\t{%3, %2, %0|%0, %2, %3} + vfmsubadd231\t{%2, %1, %0|%0, %1, %2} vfmsubadd\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmsubadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fmsubadd__mask" +(define_insn "avx512f_fmsubadd__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "0,0") - (match_operand:VF_512 2 "nonimmediate_operand" "vm,v") + (match_operand:VF_512 2 "" ",v") (neg:VF_512 - (match_operand:VF_512 3 "nonimmediate_operand" "v,vm"))] + (match_operand:VF_512 3 "" "v,"))] UNSPEC_FMADDSUB) (match_dup 1) (match_operand: 4 "register_operand" "k,k")))] "TARGET_AVX512F" "@ - vfmsubadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} - vfmsubadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" + vfmsubadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} + vfmsubadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "avx512f_fmsubadd__mask3" +(define_insn "avx512f_fmsubadd__mask3" [(set (match_operand:VF_512 0 "register_operand" "=v") (vec_merge:VF_512 (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "v") - (match_operand:VF_512 2 "nonimmediate_operand" "vm") + (match_operand:VF_512 2 "" "") (neg:VF_512 (match_operand:VF_512 3 "register_operand" "0"))] UNSPEC_FMADDSUB) (match_dup 3) (match_operand: 4 "register_operand" "k")))] "TARGET_AVX512F" - "vfmsubadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" + "vfmsubadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "isa" "fma_avx512f") (set_attr "type" "ssemuladd") (set_attr "mode" "")]) @@ -3093,13 +3107,13 @@ ;; FMA3 floating point scalar intrinsics. These merge result with ;; high-order elements from the destination register. -(define_expand "fmai_vmfmadd_" +(define_expand "fmai_vmfmadd_" [(set (match_operand:VF_128 0 "register_operand") (vec_merge:VF_128 (fma:VF_128 - (match_operand:VF_128 1 "nonimmediate_operand") - (match_operand:VF_128 2 "nonimmediate_operand") - (match_operand:VF_128 3 "nonimmediate_operand")) + (match_operand:VF_128 1 "") + (match_operand:VF_128 2 "") + (match_operand:VF_128 3 "")) (match_dup 1) (const_int 1)))] "TARGET_FMA") @@ -3108,15 +3122,15 @@ [(set (match_operand:VF_128 0 "register_operand" "=v,v") (vec_merge:VF_128 (fma:VF_128 - (match_operand:VF_128 1 "nonimmediate_operand" " 0, 0") - (match_operand:VF_128 2 "nonimmediate_operand" "vm, v") - (match_operand:VF_128 3 "nonimmediate_operand" " v,vm")) + (match_operand:VF_128 1 "" " 0, 0") + (match_operand:VF_128 2 "" ", v") + (match_operand:VF_128 3 "" " v,")) (match_dup 1) (const_int 1)))] "TARGET_FMA || TARGET_AVX512F" "@ - vfmadd132\t{%2, %3, %0|%0, %3, %2} - vfmadd213\t{%3, %2, %0|%0, %2, %3}" + vfmadd132\t{%2, %3, %0|%0, %3, %2} + vfmadd213\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "mode" "")]) @@ -3124,51 +3138,51 @@ [(set (match_operand:VF_128 0 "register_operand" "=v,v") (vec_merge:VF_128 (fma:VF_128 - (match_operand:VF_128 1 "nonimmediate_operand" " 0, 0") - (match_operand:VF_128 2 "nonimmediate_operand" "vm, v") + (match_operand:VF_128 1 "" "0,0") + (match_operand:VF_128 2 "" ",v") (neg:VF_128 - (match_operand:VF_128 3 "nonimmediate_operand" " v,vm"))) + (match_operand:VF_128 3 "" " v,"))) (match_dup 1) (const_int 1)))] "TARGET_FMA || TARGET_AVX512F" "@ - vfmsub132\t{%2, %3, %0|%0, %3, %2} - vfmsub213\t{%3, %2, %0|%0, %2, %3}" + vfmsub132\t{%2, %3, %0|%0, %3, %2} + vfmsub213\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fmai_fnmadd_" +(define_insn "*fmai_fnmadd_" [(set (match_operand:VF_128 0 "register_operand" "=v,v") (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "nonimmediate_operand" "vm, v")) - (match_operand:VF_128 1 "nonimmediate_operand" " 0, 0") - (match_operand:VF_128 3 "nonimmediate_operand" " v,vm")) + (match_operand:VF_128 2 "" ",v")) + (match_operand:VF_128 1 "" "0,0") + (match_operand:VF_128 3 "" "v,")) (match_dup 1) (const_int 1)))] "TARGET_FMA || TARGET_AVX512F" "@ - vfnmadd132\t{%2, %3, %0|%0, %3, %2} - vfnmadd213\t{%3, %2, %0|%0, %2, %3}" + vfnmadd132\t{%2, %3, %0|%0, %3, %2} + vfnmadd213\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fmai_fnmsub_" +(define_insn "*fmai_fnmsub_" [(set (match_operand:VF_128 0 "register_operand" "=v,v") (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "nonimmediate_operand" "vm, v")) - (match_operand:VF_128 1 "nonimmediate_operand" " 0, 0") + (match_operand:VF_128 2 "" ", v")) + (match_operand:VF_128 1 "" " 0, 0") (neg:VF_128 - (match_operand:VF_128 3 "nonimmediate_operand" " v,vm"))) + (match_operand:VF_128 3 "" " v,"))) (match_dup 1) (const_int 1)))] "TARGET_FMA || TARGET_AVX512F" "@ - vfnmsub132\t{%2, %3, %0|%0, %3, %2} - vfnmsub213\t{%3, %2, %0|%0, %2, %3}" + vfnmsub132\t{%2, %3, %0|%0, %3, %2} + vfnmsub213\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "mode" "")]) @@ -3289,18 +3303,18 @@ (set_attr "prefix_rep" "0") (set_attr "mode" "SF")]) -(define_insn "sse_cvtsi2ss" +(define_insn "sse_cvtsi2ss" [(set (match_operand:V4SF 0 "register_operand" "=x,x,v") (vec_merge:V4SF (vec_duplicate:V4SF - (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm"))) + (float:SF (match_operand:SI 2 "" "r,m,"))) (match_operand:V4SF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE" "@ cvtsi2ss\t{%2, %0|%0, %2} cvtsi2ss\t{%2, %0|%0, %2} - vcvtsi2ss\t{%2, %1, %0|%0, %1, %2}" + vcvtsi2ss\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseicvt") (set_attr "athlon_decode" "vector,double,*") @@ -3310,18 +3324,18 @@ (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "SF")]) -(define_insn "sse_cvtsi2ssq" +(define_insn "sse_cvtsi2ssq" [(set (match_operand:V4SF 0 "register_operand" "=x,x,v") (vec_merge:V4SF (vec_duplicate:V4SF - (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm"))) + (float:SF (match_operand:DI 2 "" "r,m,"))) (match_operand:V4SF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE && TARGET_64BIT" "@ cvtsi2ssq\t{%2, %0|%0, %2} cvtsi2ssq\t{%2, %0|%0, %2} - vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}" + vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseicvt") (set_attr "athlon_decode" "vector,double,*") @@ -3333,15 +3347,15 @@ (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "SF")]) -(define_insn "sse_cvtss2si" +(define_insn "sse_cvtss2si" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "v,m") + (match_operand:V4SF 1 "" "v,") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE" - "%vcvtss2si\t{%1, %0|%0, %k1}" + "%vcvtss2si\t{%1, %0|%0, %k1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "bdver1_decode" "double,double") @@ -3363,15 +3377,15 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) -(define_insn "sse_cvtss2siq" +(define_insn "sse_cvtss2siq" [(set (match_operand:DI 0 "register_operand" "=r,r") (unspec:DI [(vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "v,m") + (match_operand:V4SF 1 "" "v,") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE && TARGET_64BIT" - "%vcvtss2si{q}\t{%1, %0|%0, %k1}" + "%vcvtss2si{q}\t{%1, %0|%0, %k1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "bdver1_decode" "double,double") @@ -3425,50 +3439,50 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "DI")]) -(define_insn "cvtusi232" +(define_insn "cvtusi232" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (vec_duplicate:VF_128 (unsigned_float: - (match_operand:SI 2 "nonimmediate_operand" "rm"))) + (match_operand:SI 2 "" ""))) (match_operand:VF_128 1 "register_operand" "v") (const_int 1)))] - "TARGET_AVX512F" - "vcvtusi2\t{%2, %1, %0|%0, %1, %2}" + "TARGET_AVX512F && " + "vcvtusi2\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "cvtusi264" +(define_insn "cvtusi264" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (vec_duplicate:VF_128 (unsigned_float: - (match_operand:DI 2 "nonimmediate_operand" "rm"))) + (match_operand:DI 2 "" ""))) (match_operand:VF_128 1 "register_operand" "v") (const_int 1)))] "TARGET_AVX512F && TARGET_64BIT" - "vcvtusi2\t{%2, %1, %0|%0, %1, %2}" + "vcvtusi2\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "float2" +(define_insn "float2" [(set (match_operand:VF1 0 "register_operand" "=v") (float:VF1 - (match_operand: 1 "nonimmediate_operand" "vm")))] - "TARGET_SSE2 && " - "%vcvtdq2ps\t{%1, %0|%0, %1}" + (match_operand: 1 "" "")))] + "TARGET_SSE2 && && " + "%vcvtdq2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_insn "ufloatv16siv16sf2" +(define_insn "ufloatv16siv16sf2" [(set (match_operand:V16SF 0 "register_operand" "=v") (unsigned_float:V16SF - (match_operand:V16SI 1 "nonimmediate_operand" "vm")))] + (match_operand:V16SI 1 "" "")))] "TARGET_AVX512F" - "vcvtudq2ps\t{%1, %0|%0, %1}" + "vcvtudq2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "V16SF")]) @@ -3503,24 +3517,24 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_insn "avx512f_fix_notruncv16sfv16si" +(define_insn "avx512f_fix_notruncv16sfv16si" [(set (match_operand:V16SI 0 "register_operand" "=v") (unspec:V16SI - [(match_operand:V16SF 1 "nonimmediate_operand" "vm")] + [(match_operand:V16SF 1 "" "")] UNSPEC_FIX_NOTRUNC))] "TARGET_AVX512F" - "vcvtps2dq\t{%1, %0|%0, %1}" + "vcvtps2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "avx512f_ufix_notruncv16sfv16si" +(define_insn "avx512f_ufix_notruncv16sfv16si" [(set (match_operand:V16SI 0 "register_operand" "=v") (unspec:V16SI - [(match_operand:V16SF 1 "nonimmediate_operand" "vm")] + [(match_operand:V16SF 1 "" "")] UNSPEC_UNSIGNED_FIX_NOTRUNC))] "TARGET_AVX512F" - "vcvtps2udq\t{%1, %0|%0, %1}" + "vcvtps2udq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) @@ -3638,18 +3652,18 @@ (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "DF")]) -(define_insn "sse2_cvtsi2sdq" +(define_insn "sse2_cvtsi2sdq" [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") (vec_merge:V2DF (vec_duplicate:V2DF - (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm"))) + (float:DF (match_operand:DI 2 "" "r,m,"))) (match_operand:V2DF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE2 && TARGET_64BIT" "@ cvtsi2sdq\t{%2, %0|%0, %2} cvtsi2sdq\t{%2, %0|%0, %2} - vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}" + vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,direct,*") @@ -3660,28 +3674,28 @@ (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "DF")]) -(define_insn "avx512f_vcvtss2usi" +(define_insn "avx512f_vcvtss2usi" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "" "") (parallel [(const_int 0)]))] UNSPEC_UNSIGNED_FIX_NOTRUNC))] "TARGET_AVX512F" - "vcvtss2usi\t{%1, %0|%0, %1}" + "vcvtss2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "SI")]) -(define_insn "avx512f_vcvtss2usiq" +(define_insn "avx512f_vcvtss2usiq" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "" "") (parallel [(const_int 0)]))] UNSPEC_UNSIGNED_FIX_NOTRUNC))] "TARGET_AVX512F && TARGET_64BIT" - "vcvtss2usi\t{%1, %0|%0, %1}" + "vcvtss2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "DI")]) @@ -3710,28 +3724,28 @@ (set_attr "prefix" "evex") (set_attr "mode" "DI")]) -(define_insn "avx512f_vcvtsd2usi" +(define_insn "avx512f_vcvtsd2usi" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "vm") + (match_operand:V2DF 1 "" "") (parallel [(const_int 0)]))] UNSPEC_UNSIGNED_FIX_NOTRUNC))] "TARGET_AVX512F" - "vcvtsd2usi\t{%1, %0|%0, %1}" + "vcvtsd2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "SI")]) -(define_insn "avx512f_vcvtsd2usiq" +(define_insn "avx512f_vcvtsd2usiq" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "vm") + (match_operand:V2DF 1 "" "") (parallel [(const_int 0)]))] UNSPEC_UNSIGNED_FIX_NOTRUNC))] "TARGET_AVX512F && TARGET_64BIT" - "vcvtsd2usi\t{%1, %0|%0, %1}" + "vcvtsd2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "DI")]) @@ -3760,15 +3774,15 @@ (set_attr "prefix" "evex") (set_attr "mode" "DI")]) -(define_insn "sse2_cvtsd2si" +(define_insn "sse2_cvtsd2si" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "v,m") + (match_operand:V2DF 1 "" "v,") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2" - "%vcvtsd2si\t{%1, %0|%0, %q1}" + "%vcvtsd2si\t{%1, %0|%0, %q1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "bdver1_decode" "double,double") @@ -3791,15 +3805,15 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) -(define_insn "sse2_cvtsd2siq" +(define_insn "sse2_cvtsd2siq" [(set (match_operand:DI 0 "register_operand" "=r,r") (unspec:DI [(vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "v,m") + (match_operand:V2DF 1 "" "v,") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2 && TARGET_64BIT" - "%vcvtsd2si{q}\t{%1, %0|%0, %q1}" + "%vcvtsd2si{q}\t{%1, %0|%0, %q1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "bdver1_decode" "double,double") @@ -3920,13 +3934,13 @@ (set_attr "ssememalign" "64") (set_attr "mode" "V2DF")]) -(define_insn "avx512f_cvtpd2dq512" +(define_insn "avx512f_cvtpd2dq512" [(set (match_operand:V8SI 0 "register_operand" "=v") (unspec:V8SI - [(match_operand:V8DF 1 "nonimmediate_operand" "vm")] + [(match_operand:V8DF 1 "" "")] UNSPEC_FIX_NOTRUNC))] "TARGET_AVX512F" - "vcvtpd2dq\t{%1, %0|%0, %1}" + "vcvtpd2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "OI")]) @@ -3994,13 +4008,13 @@ (set_attr "athlon_decode" "vector") (set_attr "bdver1_decode" "double")]) -(define_insn "avx512f_ufix_notruncv8dfv8si" +(define_insn "avx512f_ufix_notruncv8dfv8si" [(set (match_operand:V8SI 0 "register_operand" "=v") (unspec:V8SI - [(match_operand:V8DF 1 "nonimmediate_operand" "vm")] + [(match_operand:V8DF 1 "" "")] UNSPEC_UNSIGNED_FIX_NOTRUNC))] "TARGET_AVX512F" - "vcvtpd2udq\t{%1, %0|%0, %1}" + "vcvtpd2udq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "OI")]) @@ -4116,12 +4130,12 @@ (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "DF")]) -(define_insn "avx512f_cvtpd2ps512" +(define_insn "avx512f_cvtpd2ps512" [(set (match_operand:V8SF 0 "register_operand" "=v") (float_truncate:V8SF - (match_operand:V8DF 1 "nonimmediate_operand" "vm")))] + (match_operand:V8DF 1 "" "")))] "TARGET_AVX512F" - "vcvtpd2ps\t{%1, %0|%0, %1}" + "vcvtpd2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "V8SF")]) @@ -6489,14 +6503,14 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_scalef" +(define_insn "avx512f_scalef" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "v") - (match_operand:VF_512 2 "nonimmediate_operand" "vm")] + (match_operand:VF_512 2 "" "")] UNSPEC_SCALEF))] "TARGET_AVX512F" - "%vscalef\t{%2, %1, %0|%0, %1, %2}" + "%vscalef\t{%2, %1, %0|%0, %1, %2}" [(set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -8230,22 +8244,22 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_expand "3" +(define_expand "3" [(set (match_operand:VI124_256_48_512 0 "register_operand") (maxmin:VI124_256_48_512 - (match_operand:VI124_256_48_512 1 "nonimmediate_operand") - (match_operand:VI124_256_48_512 2 "nonimmediate_operand")))] - "TARGET_AVX2 && " + (match_operand:VI124_256_48_512 1 "") + (match_operand:VI124_256_48_512 2 "")))] + "TARGET_AVX2 && && " "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*avx2_3" +(define_insn "*avx2_3" [(set (match_operand:VI124_256_48_512 0 "register_operand" "=v") (maxmin:VI124_256_48_512 - (match_operand:VI124_256_48_512 1 "nonimmediate_operand" "%v") - (match_operand:VI124_256_48_512 2 "nonimmediate_operand" "vm")))] + (match_operand:VI124_256_48_512 1 "" "%v") + (match_operand:VI124_256_48_512 2 "" "")))] "TARGET_AVX2 && ix86_binary_operator_ok (, mode, operands) - && " - "vp\t{%2, %1, %0|%0, %1, %2}" + && && " + "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_evex") @@ -12543,33 +12557,33 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "avx512er_exp2" +(define_insn "avx512er_exp2" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 - [(match_operand:VF_512 1 "nonimmediate_operand" "vm")] + [(match_operand:VF_512 1 "" "")] UNSPEC_EXP2))] "TARGET_AVX512ER" - "vexp2\t{%1, %0|%0, %1}" + "vexp2\t{%1, %0|%0, %1}" [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512er_rcp28" +(define_insn "avx512er_rcp28" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 - [(match_operand:VF_512 1 "nonimmediate_operand" "vm")] + [(match_operand:VF_512 1 "" "")] UNSPEC_RCP28))] "TARGET_AVX512ER" - "vrcp28\t{%1, %0|%0, %1}" + "vrcp28\t{%1, %0|%0, %1}" [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512er_rsqrt28" +(define_insn "avx512er_rsqrt28" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 - [(match_operand:VF_512 1 "nonimmediate_operand" "vm")] + [(match_operand:VF_512 1 "" "")] UNSPEC_RSQRT28))] "TARGET_AVX512ER" - "vrsqrt28\t{%1, %0|%0, %1}" + "vrsqrt28\t{%1, %0|%0, %1}" [(set_attr "prefix" "evex") (set_attr "mode" "")]) diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 594dc438922..b20cf20f95d 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -30,6 +30,16 @@ (define_mode_iterator SUBST_S [QI HI SI DI]) +(define_mode_iterator SUBST_A + [V16QI + V16HI V8HI + V16SI V8SI V4SI + V8DI V4DI V2DI + V16SF V8SF V4SF + V8DF V4DF V2DF + QI HI SI DI SF DF + CCFP CCFPU]) + (define_subst_attr "mask_name" "mask" "" "_mask") (define_subst_attr "mask_applied" "mask" "false" "true") (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2") @@ -87,3 +97,35 @@ (match_operand:SUBST_V 2 "const0_operand" "C") (match_operand: 3 "register_operand" "k"))) ]) + +(define_subst_attr "round_name" "round" "" "_round") +(define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4") +(define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5") +(define_subst_attr "round_mask_scalar_operand3" "mask_scalar" "%R3" "%R5") +(define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6") +(define_subst_attr "round_op2" "round" "" "%R2") +(define_subst_attr "round_op3" "round" "" "%R3") +(define_subst_attr "round_op4" "round" "" "%R4") +(define_subst_attr "round_op5" "round" "" "%R5") +(define_subst_attr "round_op6" "round" "" "%R6") +(define_subst_attr "round_mask_op2" "round" "" "") +(define_subst_attr "round_mask_op3" "round" "" "") +(define_subst_attr "round_mask_scalar_op3" "round" "" "") +(define_subst_attr "round_sd_mask_op4" "round" "" "") +(define_subst_attr "round_constraint" "round" "vm" "v") +(define_subst_attr "round_constraint2" "round" "m" "v") +(define_subst_attr "round_constraint3" "round" "rm" "r") +(define_subst_attr "round_nimm_predicate" "round" "nonimmediate_operand" "register_operand") +(define_subst_attr "round_mode512bit_condition" "round" "1" "(GET_MODE (operands[0]) == V16SFmode || GET_MODE (operands[0]) == V8DFmode)") +(define_subst_attr "round_modev4sf_condition" "round" "1" "(GET_MODE (operands[0]) == V4SFmode)") +(define_subst_attr "round_codefor" "round" "*" "") +(define_subst_attr "round_opnum" "round" "5" "6") + +(define_subst "round" + [(set (match_operand:SUBST_A 0) + (match_operand:SUBST_A 1))] + "TARGET_AVX512F" + [(parallel[ + (set (match_dup 0) + (match_dup 1)) + (unspec [(match_operand:SI 2 "const_0_to_4_operand")] UNSPEC_EMBEDDED_ROUNDING)])]) -- 2.30.2