From 06c791f89a02e96e95ecba6a09c23e84796c98ae Mon Sep 17 00:00:00 2001
From: Tobias Platen <tplaten@posteo.de>
Date: Sun, 11 Jul 2021 17:50:25 +0200
Subject: [PATCH] implement pi_dcbz

---
 src/soc/config/test/test_pi2ls.py       | 27 +++++++++++++++++++++++++
 src/soc/experiment/test/test_dcbz_pi.py | 13 +++++++-----
 2 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py
index eb20177c..7da250f3 100644
--- a/src/soc/config/test/test_pi2ls.py
+++ b/src/soc/config/test/test_pi2ls.py
@@ -61,9 +61,36 @@ def pi_st(port1, addr, data, datalen, msr_pr=0):
     yield port1.st.ok.eq(0)
     yield from wait_busy(port1, True)    # wait while busy
 
+# copy of pi_st
+def pi_dcbz(port1, addr, data, datalen, msr_pr=0):
+
+    # have to wait until not busy
+    yield from wait_busy(port1, no=False)    # wait until not busy
+
+    # set up a ST on the port.  address first:
+    yield port1.is_st_i.eq(1)  # indicate ST
+    yield port1.data_len.eq(datalen)  # ST length (1/2/4/8)
+    yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
+
+    yield port1.is_dcbz.eq(1) # set dcbz
+
+    yield port1.addr.data.eq(addr)  # set address
+    yield port1.addr.ok.eq(1)  # set ok
+    yield Settle()
+    yield from wait_addr(port1)             # wait until addr ok
+    # yield # not needed, just for checking
+    # yield # not needed, just for checking
+    # assert "ST" for one cycle (required by the API)
+    yield port1.st.data.eq(data)
+    yield port1.st.ok.eq(1)
+    yield
+    yield port1.st.ok.eq(0)
+    yield from wait_busy(port1, True)    # wait while busy
+
     # can go straight to reset.
     yield port1.is_st_i.eq(0)  # end
     yield port1.addr.ok.eq(0)  # set !ok
+    yield port1.is_dcbz.eq(0)  # reset dcbz too
 
 
 def pi_ld(port1, addr, datalen, msr_pr=0):
diff --git a/src/soc/experiment/test/test_dcbz_pi.py b/src/soc/experiment/test/test_dcbz_pi.py
index a49d95da..cbacf4e1 100644
--- a/src/soc/experiment/test/test_dcbz_pi.py
+++ b/src/soc/experiment/test/test_dcbz_pi.py
@@ -15,7 +15,7 @@ else:
     from nmigen.sim.cxxsim import Simulator, Delay, Settle
 from nmutil.util import wrap
 
-from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
+from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst, pi_dcbz
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.config.loadstore import ConfigMemoryPortInterface
 
@@ -121,9 +121,12 @@ def _test_dcbz_addr_zero(dut, mem):
     yield mmu.rin.prtbl.eq(0x1000000) # set process table
     yield
 
-    ###### TODO
-    #yield from pi_dcbz(pi, addr, data, 8, msr_pr=1)
-    #yield
+    addr = 0
+    data = 0 # FIXME
+    # size ==, msr_pr TODO
+
+    yield from pi_dcbz(pi, addr, data, 8, msr_pr=1)
+    yield
 
     yield
     stop = True
@@ -159,7 +162,7 @@ def test_dcbz_addr_zero():
 
     sim.add_sync_process(wrap(_test_dcbz_addr_zero(m, mem)))
     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
-    with sim.write_vcd('test_ldst_pi_random2.vcd'):
+    with sim.write_vcd('test_dcbz_addr_zero.vcd'):
         sim.run()
 
 if __name__ == '__main__':
-- 
2.30.2