From 06cf3edb90bd70ca9cf63c1ff81de400893c7d56 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 20 Sep 2022 13:44:20 +0100
Subject: [PATCH]

---
 openpower/sv/overview.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 758a64260..28ca22659 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -267,7 +267,7 @@ effectively the same as "no predicate".
 
     function op_add(RT, RA, RB) # add not VADD!
       int id=0, irs1=0, irs2=0;
-      predval = get_pred_val(FALSE, rd);
+      predval = get_pred_val(FALSE, RT); # dest mask
       for i = 0 to VL-1:
         if (predval & 1<<i) # predication bit test
            ireg[RT+id] <= ireg[RA+irs1] + ireg[RB+irs2];
-- 
2.30.2