From 06d08064946af108f902609a67b5aa16a6d23317 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 23 Sep 2019 15:57:14 +0200 Subject: [PATCH] soc_core: set csr to 0x00000000 when there is no wishbone --- litex/soc/integration/soc_core.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 152a4a2c..512d0dc0 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -205,6 +205,9 @@ class SoCCore(Module): if cpu_type == "None": cpu_type = None + if not with_wishbone: + self.soc_mem_map["csr"] = 0x00000000 + self.cpu_type = cpu_type self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant) -- 2.30.2