From 06d55a412e8d67557902f6f447c1eda214d4b65a Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Wed, 25 Mar 2020 14:24:04 +0100 Subject: [PATCH] =?utf8?q?periph.=5Fevent=20=E2=86=92=20periph.event?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- lambdasoc/periph/__init__.py | 1 + lambdasoc/periph/base.py | 2 +- lambdasoc/periph/{_event.py => event.py} | 0 lambdasoc/test/test_periph_event.py | 2 +- 4 files changed, 3 insertions(+), 2 deletions(-) rename lambdasoc/periph/{_event.py => event.py} (100%) diff --git a/lambdasoc/periph/__init__.py b/lambdasoc/periph/__init__.py index 9b5ed21..511f0c1 100644 --- a/lambdasoc/periph/__init__.py +++ b/lambdasoc/periph/__init__.py @@ -1 +1,2 @@ from .base import * +from .event import * diff --git a/lambdasoc/periph/base.py b/lambdasoc/periph/base.py index 6101946..8789ee3 100644 --- a/lambdasoc/periph/base.py +++ b/lambdasoc/periph/base.py @@ -7,7 +7,7 @@ from nmigen_soc.memory import MemoryMap from nmigen_soc.csr.wishbone import WishboneCSRBridge -from ._event import * +from .event import * __all__ = ["Peripheral", "CSRBank", "PeripheralBridge"] diff --git a/lambdasoc/periph/_event.py b/lambdasoc/periph/event.py similarity index 100% rename from lambdasoc/periph/_event.py rename to lambdasoc/periph/event.py diff --git a/lambdasoc/test/test_periph_event.py b/lambdasoc/test/test_periph_event.py index 4934af7..69aacf2 100644 --- a/lambdasoc/test/test_periph_event.py +++ b/lambdasoc/test/test_periph_event.py @@ -4,7 +4,7 @@ import unittest from nmigen import * from nmigen.back.pysim import * -from ..periph._event import * +from ..periph.event import * def simulation_test(dut, process): -- 2.30.2