From 06da4a3bfe2cd707d4f6dc504e77a572c1f10f33 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 26 Mar 2020 12:59:16 +0000 Subject: [PATCH] Re: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V --- 30/cd28bf0d25bc3bad37d035774454032b75c1a8 | 88 +++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 30/cd28bf0d25bc3bad37d035774454032b75c1a8 diff --git a/30/cd28bf0d25bc3bad37d035774454032b75c1a8 b/30/cd28bf0d25bc3bad37d035774454032b75c1a8 new file mode 100644 index 0000000..2ef2fbf --- /dev/null +++ b/30/cd28bf0d25bc3bad37d035774454032b75c1a8 @@ -0,0 +1,88 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Thu, 26 Mar 2020 12:59:40 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jHS6m-0006Tk-4R; Thu, 26 Mar 2020 12:59:40 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jHS6l-0006Te-C2 + for libre-riscv-dev@lists.libre-riscv.org; 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