From 06e9b8ef0f4886d6aaf7bc381c0f97c2cb13bcbc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Jul 2020 15:05:05 +0100 Subject: [PATCH] missing conversion of DIV to Div --- src/soc/fu/compunits/compunits.py | 10 +++++----- src/soc/fu/mul/pipe_data.py | 6 +++--- src/soc/fu/mul/pre_stage.py | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 55210173..7ee00487 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -71,8 +71,8 @@ from soc.fu.spr.pipe_data import SPRPipeSpec from soc.fu.trap.pipeline import TrapBasePipe from soc.fu.trap.pipe_data import TrapPipeSpec -from soc.fu.div.pipeline import DIVBasePipe -from soc.fu.div.pipe_data import DIVPipeSpec +from soc.fu.div.pipeline import DivBasePipe +from soc.fu.div.pipe_data import DivPipeSpec from soc.fu.mul.pipeline import MulBasePipe from soc.fu.mul.pipe_data import MulPipeSpec @@ -147,10 +147,10 @@ class ShiftRotFunctionUnit(FunctionUnitBaseSingle): def __init__(self, idx): super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe, idx) -class DIVFunctionUnit(FunctionUnitBaseSingle): +class DivFunctionUnit(FunctionUnitBaseSingle): fnunit = Function.DIV def __init__(self, idx): - super().__init__(DIVPipeSpec, DIVBasePipe, idx) + super().__init__(DivPipeSpec, DivBasePipe, idx) class MulFunctionUnit(FunctionUnitBaseSingle): fnunit = Function.MUL @@ -209,7 +209,7 @@ class AllFunctionUnits(Elaboratable): 'branch': BranchFunctionUnit, 'trap': TrapFunctionUnit, 'spr': SPRFunctionUnit, - 'div': DIVFunctionUnit, + 'div': DivFunctionUnit, 'mul': MulFunctionUnit, 'logical': LogicalFunctionUnit, 'shiftrot': ShiftRotFunctionUnit, diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py index 3a7abe37..bb77c5ce 100644 --- a/src/soc/fu/mul/pipe_data.py +++ b/src/soc/fu/mul/pipe_data.py @@ -1,10 +1,10 @@ from soc.fu.mul.mul_input_record import CompMULOpSubset from soc.fu.pipe_data import IntegerData, CommonPipeSpec -from soc.fu.div.pipe_data import DIVInputData, DivMulOutputData +from soc.fu.div.pipe_data import DivInputData, DivMulOutputData from nmigen import Signal -class MulIntermediateData(DIVInputData): +class MulIntermediateData(DivInputData): def __init__(self, pspec): super().__init__(pspec) @@ -27,5 +27,5 @@ class MulOutputData(IntegerData): class MulPipeSpec(CommonPipeSpec): - regspec = (DIVInputData.regspec, DivMulOutputData.regspec) + regspec = (DivInputData.regspec, DivMulOutputData.regspec) opsubsetkls = CompMULOpSubset diff --git a/src/soc/fu/mul/pre_stage.py b/src/soc/fu/mul/pre_stage.py index 94563874..f22964dd 100644 --- a/src/soc/fu/mul/pre_stage.py +++ b/src/soc/fu/mul/pre_stage.py @@ -2,7 +2,7 @@ from nmigen import (Module, Signal, Mux) from nmutil.pipemodbase import PipeModBase -from soc.fu.div.pipe_data import DIVInputData +from soc.fu.div.pipe_data import DivInputData from soc.fu.mul.pipe_data import MulIntermediateData from ieee754.part.partsig import PartitionedSignal from nmutil.util import eq32 @@ -12,7 +12,7 @@ class MulMainStage1(PipeModBase): super().__init__(pspec, "mul1") def ispec(self): - return DIVInputData(self.pspec) # defines pipeline stage input format + return DivInputData(self.pspec) # defines pipeline stage input format def ospec(self): return MulIntermediateData(self.pspec) # pipeline stage output format -- 2.30.2