From 06ea3e0cfb92ca2c74aad2cf6d1d0005d38b7fee Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 11 Sep 2022 12:50:11 +0100 Subject: [PATCH] move footnote --- openpower/sv/rfc/ls001.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 75dfc0655..afcdac878 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -123,7 +123,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures. * No new Interrupt types are required. (**No modifications to existing Power ISA are required either**). * GPR FPR and CR Field Register numbers are extended to 128. A future - version may extend to 256 or beyond or also extend VSX[^extend][^futurevsx] + version may extend to 256 or beyond[^extend] or also extend VSX[^futurevsx] * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO) * Another 24-bit (a second 2-bit XO) is needed for a planned future encoding, currently named "SVP64-Single" [^likeext001] -- 2.30.2