From 07102064ba17746bebf09668c6be80c953e3a612 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 16 Sep 2022 12:17:55 +0100 Subject: [PATCH] clarify basic principle --- openpower/sv/rfc/Makefile | 4 ++-- openpower/sv/rfc/ls001.mdwn | 11 ++++++----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/openpower/sv/rfc/Makefile b/openpower/sv/rfc/Makefile index 23df8bb3b..bb2137c52 100644 --- a/openpower/sv/rfc/Makefile +++ b/openpower/sv/rfc/Makefile @@ -4,8 +4,8 @@ ls001.pdf: ls001.mdwn pandoc \ -V margin-top=0.9in \ -V margin-bottom=0.9in \ - -V margin-left=0.5in \ - -V margin-right=0.5in \ + -V margin-left=0.4in \ + -V margin-right=0.4in \ -V fontsize=9pt \ -V papersize=legal \ -V linkcolor=blue \ diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 8dd3d42bb..6ff623b83 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -69,15 +69,16 @@ Branch. # Basic principle -The inspiration for this came from the fact that on examination of every +The inspiration for Simple-V came from the fact that on examination of every Vector ISA pseudocode encountered the Vector operations were expressed as a for-loop on a Scalar element operation, and then both a Scalar **and** a Vector instruction was added. -It felt natural to separate the two at both the ISA and the Hardware Level +With Zero-Overhead Looping *already* being mainstream in DSPs for over three +decades it felt natural to separate the looping at both the ISA and +the Hardware Level and thus provide only Scalar instructions (instantly halving the number -of instructions), leaving it up to implementors -to implement Superscalar and Multi-Issue Micro-architectures at their -discretion. +of instructions), but rather than go the VLIW route (TI MSP Series) +keep closely to existing Power ISA standard Scalar execution. Thus the basic principle of Simple-V is to provide a Precise-Interruptible Zero-Overhead Loop system[^zolc] with associated register "offsetting" -- 2.30.2