From 0729b3a059b1991405de8b345b3130499c874ef5 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 31 Oct 2018 13:29:35 +0000 Subject: [PATCH] ulx3s: Connect SDRAM clock Signed-off-by: David Shah --- litex/boards/targets/ulx3s.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 6d8a4e07..af1aa19e 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -45,6 +45,8 @@ class _CRG(Module): o_Z=new_sdram_ps_clk) sdram_ps_clk = new_sdram_ps_clk self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk) + sdram_clock = platform.request("sdram_clock") + self.comb += sdram_clock.eq(sdram_ps_clk) # Stop ESP32 from resetting FPGA wifi_gpio0 = platform.request("wifi_gpio0") -- 2.30.2