From 072dc08b52570be32384992fdd4821355b403033 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 1 Apr 2023 01:23:26 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 3085109f1..26d966325 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -671,3 +671,17 @@ for LDST Immediate only having `zz`. Simple-V is powerful but it cannot do everything! There is just not enough space and so some compromises had to be made. + +# sv.mtcr on entire 64-bit Condition Register + +Normally, CR operations are either bit-based (where the element numbering actually +applies to the CR Field) or field-based in which case the elements are still +fields. The `sv.mtcr` and other instructions are actually full 64-bit Condition +*Register* operations and are therefore qualified as Normal/Arithmetic not +CRops. + +This is to save on both Vector Length (VL of 16 is sufficient) as well as +complexity in the Hazard Management when context-switching CR fields, as the +entire batch of 128 CR Fields may be transferred to 8 GPRs with a VL of 16 +and elwidth overriding of 32. Truncation is sufficent, dropping the top 32 bits +of the Condition Register(s) which are always zero anywy. -- 2.30.2