From 074377e9c1cd103e86e79ace2370ed62f230046f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 19 Jun 2021 12:32:06 +0100 Subject: [PATCH] different mapreduce modes --- openpower/sv/svp64.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 1453dd9e9..b6502f9ce 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -203,7 +203,8 @@ The Mode table for operations except LD/ST is laid out as follows: | 0-1 | 2 | 3 4 | description | | --- | --- |---------|-------------------------- | | 00 | 0 | dz sz | normal mode | -| 00 | 1 | dz RG | reduce mode (mapreduce), SUBVL=1 | +| 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | +| 00 | 1 | 1 CRM | parallel reduce mode (mapreduce), SUBVL=1 | | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | | 01 | inv | dz RC1 | Rc=0: ffirst z/nonz | @@ -217,6 +218,7 @@ Fields: * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1) * **RG** inverts the Vector Loop order (VL-1 downto 0) rather than the normal 0..VL-1 +* **CRM** affects the CR on reduce mode when Rc=1 * **SVM** sets "subvector" reduce mode * **N** sets signed/unsigned saturation. **RC1** as if Rc=1, stores CRs *but not the result* -- 2.30.2