From 0750c1e02fe3655d8b4bf0c81b87879e9aea3192 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 15 Oct 2020 13:25:49 +0100 Subject: [PATCH] enable/disable litex irqs based on variant name --- libreriscv | 2 +- src/soc/litex/florent/libresoc/core.py | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/libreriscv b/libreriscv index 1f4b308f..f0f302d8 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit 1f4b308f975418595a0858cd37e7e66f2fe7244d +Subproject commit f0f302d80683c9b68fc9b13dac9f590ae1937232 diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index f72e2f07..3bc76798 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -148,7 +148,10 @@ class LibreSoC(CPU): self.platform = platform self.variant = variant self.reset = Signal() - self.interrupt = Signal(16) + irq_en = "noirq" not in variant + + if irq_en: + self.interrupt = Signal(16) if variant == "standard32": self.data_width = 32 @@ -200,11 +203,12 @@ class LibreSoC(CPU): o_memerr_o = Signal(), # not connected o_pc_o = Signal(64), # not connected - # interrupts - i_int_level_i = self.interrupt, - ) + if irq_en: + # interrupts + self.cpu_params['i_int_level_i'] = self.interrupt + if jtag_en: self.cpu_params.update(dict( # JTAG Debug bus -- 2.30.2