From 075ea32e485252f0376ee7bbc84ed436e9eb4b65 Mon Sep 17 00:00:00 2001
From: Gert Wollny <gert.wollny@collabora.com>
Date: Sun, 12 Apr 2020 16:59:05 +0200
Subject: [PATCH] r600/sfn: Add TF write instruction

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
---
 .../drivers/r600/sfn/sfn_instruction_base.h   |  1 +
 .../drivers/r600/sfn/sfn_instruction_gds.cpp  | 29 ++++++++++++++
 .../drivers/r600/sfn/sfn_instruction_gds.h    | 14 +++++++
 .../drivers/r600/sfn/sfn_ir_to_assembly.cpp   | 39 +++++++++++++++++++
 4 files changed, 83 insertions(+)

diff --git a/src/gallium/drivers/r600/sfn/sfn_instruction_base.h b/src/gallium/drivers/r600/sfn/sfn_instruction_base.h
index f7042b378e2..4986fa9728c 100644
--- a/src/gallium/drivers/r600/sfn/sfn_instruction_base.h
+++ b/src/gallium/drivers/r600/sfn/sfn_instruction_base.h
@@ -90,6 +90,7 @@ public:
       mem_wr_scratch,
       gds,
       rat,
+      tf_write,
       block,
       unknown
    };
diff --git a/src/gallium/drivers/r600/sfn/sfn_instruction_gds.cpp b/src/gallium/drivers/r600/sfn/sfn_instruction_gds.cpp
index 2fd8c7292a3..9c1207b7eb7 100644
--- a/src/gallium/drivers/r600/sfn/sfn_instruction_gds.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_instruction_gds.cpp
@@ -142,4 +142,33 @@ RatInstruction::ERatOp RatInstruction::opcode(nir_intrinsic_op opcode)
    }
 }
 
+GDSStoreTessFactor::GDSStoreTessFactor(GPRVector& value):
+   Instruction(tf_write),
+   m_value(value)
+{
+   add_remappable_src_value(&m_value);
+}
+
+void GDSStoreTessFactor::replace_values(const ValueSet& candiates, PValue new_value)
+{
+   for (auto& c: candiates) {
+      for (int i = 0; i < 4; ++i) {
+         if (*c == *m_value[i])
+            m_value[i] = new_value;
+      }
+   }
+}
+
+
+bool GDSStoreTessFactor::is_equal_to(const Instruction& lhs) const
+{
+   auto& other = static_cast<const GDSStoreTessFactor&>(lhs);
+   return m_value == other.m_value;
+}
+
+void GDSStoreTessFactor::do_print(std::ostream& os) const
+{
+   os << "TF_WRITE " << m_value;
+}
+
 }
diff --git a/src/gallium/drivers/r600/sfn/sfn_instruction_gds.h b/src/gallium/drivers/r600/sfn/sfn_instruction_gds.h
index 1499d7fb736..72708d09990 100644
--- a/src/gallium/drivers/r600/sfn/sfn_instruction_gds.h
+++ b/src/gallium/drivers/r600/sfn/sfn_instruction_gds.h
@@ -190,6 +190,20 @@ private:
 
 };
 
+class GDSStoreTessFactor : public Instruction {
+public:
+      GDSStoreTessFactor(GPRVector& value);
+      int sel() const {return m_value.sel();}
+      int chan(int i ) const {return m_value.chan_i(i);}
+
+      void replace_values(const ValueSet& candiates, PValue new_value) override;
+private:
+      bool is_equal_to(const Instruction& lhs) const override;
+      void do_print(std::ostream& os) const override;
+
+      GPRVector m_value;
+};
+
 }
 
 #endif // SFN_GDSINSTR_H
diff --git a/src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp b/src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp
index 762439a33f2..9794057df93 100644
--- a/src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp
@@ -67,6 +67,7 @@ private:
    bool emit_rat(const RatInstruction& instr);
    bool emit_ldswrite(const LDSWriteInstruction& instr);
    bool emit_ldsread(const LDSReadInstruction& instr);
+   bool emit_tf_write(const GDSStoreTessFactor& instr);
 
    bool emit_load_addr(PValue addr);
    bool emit_fs_pixel_export(const ExportInstruction & exi);
@@ -196,6 +197,8 @@ bool AssemblyFromShaderLegacyImpl::emit(const Instruction::Pointer i)
       return emit_ldswrite(static_cast<const LDSWriteInstruction&>(*i));
    case Instruction::lds_read:
       return emit_ldsread(static_cast<const LDSReadInstruction&>(*i));
+   case Instruction::tf_write:
+      return emit_tf_write(static_cast<const GDSStoreTessFactor&>(*i));
    default:
       return false;
    }
@@ -950,6 +953,42 @@ bool AssemblyFromShaderLegacyImpl::emit_gds(const GDSInstr& instr)
    return true;
 }
 
+bool AssemblyFromShaderLegacyImpl::emit_tf_write(const GDSStoreTessFactor& instr)
+{
+   struct r600_bytecode_gds gds;
+
+   memset(&gds, 0, sizeof(struct r600_bytecode_gds));
+   gds.src_gpr = instr.sel();
+   gds.src_sel_x = instr.chan(0);
+   gds.src_sel_y = instr.chan(1);
+   gds.src_sel_z = 4;
+   gds.dst_sel_x = 7;
+   gds.dst_sel_y = 7;
+   gds.dst_sel_z = 7;
+   gds.dst_sel_w = 7;
+   gds.op = FETCH_OP_TF_WRITE;
+
+   if (r600_bytecode_add_gds(m_bc, &gds) != 0)
+         return false;
+
+   if (instr.chan(2) != 7) {
+      memset(&gds, 0, sizeof(struct r600_bytecode_gds));
+      gds.src_gpr = instr.sel();
+      gds.src_sel_x = instr.chan(2);
+      gds.src_sel_y = instr.chan(3);
+      gds.src_sel_z = 4;
+      gds.dst_sel_x = 7;
+      gds.dst_sel_y = 7;
+      gds.dst_sel_z = 7;
+      gds.dst_sel_w = 7;
+      gds.op = FETCH_OP_TF_WRITE;
+
+      if (r600_bytecode_add_gds(m_bc, &gds))
+         return false;
+   }
+   return true;
+}
+
 bool AssemblyFromShaderLegacyImpl::emit_ldswrite(const LDSWriteInstruction& instr)
 {
    r600_bytecode_alu alu;
-- 
2.30.2