From 0769d538e5141cb75c9d49f480baa70178534d2e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Jun 2020 06:39:53 +0100 Subject: [PATCH] got test_issuer FSM operating. bit of a hack --- src/soc/decoder/isa/caller.py | 1 + src/soc/simple/core.py | 14 ++++++++------ src/soc/simple/test/test_issuer.py | 6 +++++- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 1ed3cc90..af28a996 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -321,6 +321,7 @@ class ISACaller: imm = yield self.dec2.e.imm_data.data inputs.append(SelectableInt(imm, 64)) assert len(outputs) >= 1 + print ("handle_overflow", inputs, outputs) if len(inputs) >= 2: output = outputs[0] diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 99622336..cb234628 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -352,10 +352,11 @@ class TestIssuer(Elaboratable): current_insn = Signal(32) # current fetched instruction (note sync) current_pc = Signal(64) # current PC (note it is reset/sync) comb += self.pc_o.eq(current_pc) + ilatch = Signal(32) # next instruction (+4 on current) nia = Signal(64, reset_less=True) - comb += nia.eq(current_insn + 4) + comb += nia.eq(current_pc + 4) # temporaries core_busy_o = core.busy_o # core is busy @@ -382,24 +383,25 @@ class TestIssuer(Elaboratable): # capture the PC and also drop it into Insn Memory # we have joined a pair of combinatorial memory # lookups together. this is Generally Bad. - sync += current_pc.eq(pc) - comb += self.i_rd.addr.eq(pc) - #comb += self.i_rd.en.eq(1) # comb-read (no need to set) - sync += current_insn.eq(self.i_rd.data) + comb += self.i_rd.addr.eq(pc[2:]) # ignore last 2 bits + comb += current_insn.eq(self.i_rd.data) + comb += current_pc.eq(pc) m.next = "INSN_READ" # move to "issue" phase # got the instruction: start issue with m.State("INSN_READ"): + comb += current_insn.eq(self.i_rd.data) comb += core_ivalid_i.eq(1) # say instruction is valid comb += core_issue_i.eq(1) # and issued (ivalid_i redundant) comb += core_be_i.eq(0) # little-endian mode comb += core_opcode_i.eq(current_insn) # actual opcode + sync += ilatch.eq(current_insn) m.next = "INSN_ACTIVE" # move to "wait for completion" phase # instruction started: must wait till it finishes with m.State("INSN_ACTIVE"): comb += core_ivalid_i.eq(1) # say instruction is valid - comb += core_opcode_i.eq(current_insn) # actual opcode + comb += core_opcode_i.eq(ilatch) # actual opcode #sync += core_issue_i.eq(0) # issue raises for only one cycle with m.If(~core_busy_o): # instruction done! #sync += core_ivalid_i.eq(0) # say instruction is invalid diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index cd07b500..54a41b2a 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -53,6 +53,7 @@ class TestRunner(FHDLTestCase): m = Module() comb = m.d.comb go_insn_i = Signal() + pc_i = Signal(32) m.submodules.issuer = issuer = TestIssuer() imem = issuer.imem.mem @@ -60,6 +61,7 @@ class TestRunner(FHDLTestCase): pdecode2 = core.pdecode2 l0 = core.l0 + comb += issuer.pc_i.data.eq(pc_i) comb += issuer.go_insn_i.eq(go_insn_i) # nmigen Simulation @@ -83,7 +85,7 @@ class TestRunner(FHDLTestCase): yield from setup_test_memory(l0, sim) yield from setup_regs(core, test) - yield issuer.pc_i.data.eq(pc) + yield pc_i.eq(pc) yield issuer.pc_i.ok.eq(1) index = sim.pc.CIA.value//4 @@ -115,6 +117,8 @@ class TestRunner(FHDLTestCase): # Memory check yield from check_sim_memory(self, l0, sim, code) + yield + sim.add_sync_process(process) with sim.write_vcd("issuer_simulator.vcd", traces=[]): -- 2.30.2