From 077bc8519679e16b38ef97240e5dcb635bc3dd37 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 19 Nov 2019 10:20:07 +0000
Subject: [PATCH] arch-arm: Remove unnecessary RegIndex set for VSTR VFP inst

vd index is already set at the beginning of the
decodeExtensionRegLoadStore function.

Change-Id: Ic8cea43cf3a60881823195ef6da0bbda6940f1cf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23950
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
---
 src/arch/arm/isa/formats/fp.isa | 21 ++++++---------------
 1 file changed, 6 insertions(+), 15 deletions(-)

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index df9c9f2c0..0b99cc6c3 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -1901,14 +1901,8 @@ let {{
         const uint32_t offset = bits(machInst, 7, 0);
         const bool single = (bits(machInst, 8) == 0);
         const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
-        RegIndex vd;
-        if (single) {
-            vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
-                                      bits(machInst, 22));
-        } else {
-            vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
-                                      (bits(machInst, 22) << 5));
-        }
+        RegIndex vd = decodeFpVd(machInst, single ? 0x2 : 0x3, false);
+
         switch (bits(opcode, 4, 3)) {
           case 0x0:
             if (bits(opcode, 4, 1) == 0x2 &&
@@ -1982,13 +1976,6 @@ let {{
           case 0x3:
             const bool up = (bits(machInst, 23) == 1);
             const uint32_t imm = bits(machInst, 7, 0) << 2;
-            if (single) {
-                vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
-                                          (bits(machInst, 22)));
-            } else {
-                vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
-                                          (bits(machInst, 22) << 5));
-            }
             if (bits(opcode, 1, 0) == 0x0) {
                 if (single) {
                     if (up) {
@@ -2047,6 +2034,10 @@ let {{
     header_output = '''
     StaticInstPtr
     decodeShortFpTransfer(ExtMachInst machInst);
+
+    IntRegIndex decodeFpVd(ExtMachInst machInst, uint32_t size, bool isInt);
+    IntRegIndex decodeFpVm(ExtMachInst machInst, uint32_t size, bool isInt);
+    IntRegIndex decodeFpVn(ExtMachInst machInst, uint32_t size);
     '''
     decoder_output = '''
     IntRegIndex decodeFpVd(ExtMachInst machInst, uint32_t size, bool isInt)
-- 
2.30.2