From 07a38de7ceed3080f6f95912624d7e01ae352b6d Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Wed, 26 Sep 2018 01:31:22 +0200 Subject: [PATCH] rs6000: Simplify "switch (which_alternative)" patterns A few of the rs6000 patterns use C code as output control string, where that code is just a "switch (which_alternative)" with all alternatives returning a constant string or just the result of a function call as template. Write such cases as just a list of templates, with the few pieces that are C code preceded by "*". * config/rs6000/altivec.md (*altivec_mov): Write the output control string as a list of templates instead of as C code. (*altivec_movti): Ditto. * config/rs6000/darwin.md (movdf_low_di): Ditto. From-SVN: r264587 --- gcc/ChangeLog | 7 ++++++ gcc/config/rs6000/altivec.md | 48 ++++++++++++++---------------------- gcc/config/rs6000/darwin.md | 14 +++-------- 3 files changed, 29 insertions(+), 40 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d43e6d682cc..54d9ecfe36e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-09-25 Segher Boessenkool + + * config/rs6000/altivec.md (*altivec_mov): Write the output + control string as a list of templates instead of as C code. + (*altivec_movti): Ditto. + * config/rs6000/darwin.md (movdf_low_di): Ditto. + 2018-09-25 Jim Wilson * config/riscv/riscv.c (riscv_split_symbol): Mark auipc label as weak diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 345be09ceff..f37ad5a59b0 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -245,21 +245,16 @@ "VECTOR_MEM_ALTIVEC_P (mode) && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" -{ - switch (which_alternative) - { - case 0: return "stvx %1,%y0"; - case 1: return "lvx %0,%y1"; - case 2: return "vor %0,%1,%1"; - case 3: return "#"; - case 4: return "#"; - case 5: return "#"; - case 6: return "vxor %0,%0,%0"; - case 7: return output_vec_const_move (operands); - case 8: return "#"; - default: gcc_unreachable (); - } -} + "@ + stvx %1,%y0 + lvx %0,%y1 + vor %0,%1,%1 + # + # + # + vxor %0,%0,%0 + * return output_vec_const_move (operands); + #" [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*,*") (set_attr "length" "4,4,4,20,20,20,4,8,32")]) @@ -272,20 +267,15 @@ "VECTOR_MEM_ALTIVEC_P (TImode) && (register_operand (operands[0], TImode) || register_operand (operands[1], TImode))" -{ - switch (which_alternative) - { - case 0: return "stvx %1,%y0"; - case 1: return "lvx %0,%y1"; - case 2: return "vor %0,%1,%1"; - case 3: return "#"; - case 4: return "#"; - case 5: return "#"; - case 6: return "vxor %0,%0,%0"; - case 7: return output_vec_const_move (operands); - default: gcc_unreachable (); - } -} + "@ + stvx %1,%y0 + lvx %0,%y1 + vor %0,%1,%1 + # + # + # + vxor %0,%0,%0 + * return output_vec_const_move (operands);" [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*")]) ;; Load up a vector with the most significant bit set by loading up -1 and diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index 37acb312b4b..2d6d1ca57dd 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -60,17 +60,9 @@ You should have received a copy of the GNU General Public License (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") (match_operand 2 "" ""))))] "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT" -{ - switch (which_alternative) - { - case 0: - return "lfd %0,lo16(%2)(%1)"; - case 1: - return "ld %0,lo16(%2)(%1)"; - default: - gcc_unreachable (); - } -} + "@ + lfd %0,lo16(%2)(%1) + ld %0,lo16(%2)(%1)" [(set_attr "type" "load")]) (define_insn "movdf_low_st_si" -- 2.30.2