From 07a8e696ce47e9941559c66e1ef5b6d9425c784b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 6 Aug 2020 13:32:48 +0200 Subject: [PATCH] cpu/vexriscv_smp Add --with-coherent-dma --- litex/soc/cores/cpu/vexriscv_smp/core.py | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 758f6b16..6ed88151 100644 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -44,13 +44,15 @@ class VexRiscvSMP(CPU): @staticmethod def args_fill(parser): - parser.add_argument("--cpu-count", default=1, help="") - parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width") - parser.add_argument("--icache-width", default=None, help="L1 instruction cache bus width") - parser.add_argument("--dcache-size", default=None, help="L1 data cache size in byte per CPU") - parser.add_argument("--dcache-ways", default=None, help="L1 data cache ways per CPU") - parser.add_argument("--icache-size", default=None, help="L1 instruction cache size in byte per CPU") - parser.add_argument("--icache-ways", default=None, help="L1 instruction cache ways per CPU") + parser.add_argument("--cpu-count", default=1, help="") + parser.add_argument("--with-coherent-dma", action='store_true', help="") + parser.add_argument("--without-coherent-dma", action='store_true', help="") + parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width") + parser.add_argument("--icache-width", default=None, help="L1 instruction cache bus width") + parser.add_argument("--dcache-size", default=None, help="L1 data cache size in byte per CPU") + parser.add_argument("--dcache-ways", default=None, help="L1 data cache ways per CPU") + parser.add_argument("--icache-size", default=None, help="L1 instruction cache size in byte per CPU") + parser.add_argument("--icache-ways", default=None, help="L1 instruction cache ways per CPU") @staticmethod @@ -64,6 +66,8 @@ class VexRiscvSMP(CPU): VexRiscvSMP.dcache_ways = 2 VexRiscvSMP.icache_ways = 2 VexRiscvSMP.coherent_dma = True + if(args.with_coherent_dma): VexRiscvSMP.coherent_dma = bool(True) + if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False) if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width) if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width) if(args.icache_width): VexRiscvSMP.dcache_size = int(args.dcache_size) -- 2.30.2