From 07b5e59c34dcfc00c6ec15e2ea183cc9d914e62a Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 3 Sep 2022 12:16:08 +0100 Subject: [PATCH] rename normal to simple mode in ALU RM mode --- openpower/sv/normal.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 9382fd0a2..817c41367 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -23,7 +23,7 @@ functionality. Some of these alterations are element-based (saturation), others [[sv/cr_ops]] and [[sv/branches]] are covered separately: the following Modes apply to Arithmetic and Logical SVP64 operations: -* **normal** mode is straight vectorisation. no augmentations: the vector comprises an array of independently created results. +* **simple** mode is straight vectorisation. no augmentations: the vector comprises an array of independently created results. * **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria. *VL is altered as a result*. * **sat mode** or saturation: clamps each element result to a min/max rather than overflows / wraps. allows signed and unsigned clamping for both INT @@ -45,7 +45,7 @@ The Mode table for Arithmetic and Logical operations | 0-1 | 2 | 3 4 | description | | --- | --- |---------|-------------------------- | -| 00 | 0 | dz sz | normal mode | +| 00 | 0 | dz sz | simple mode | | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | | 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | | 00 | 1 | SVM 0 | subvector reduce mode, SUBVL>1 | -- 2.30.2