From 07c33279c2c9bf5c907375ad056b1c102e6e4718 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 20 Oct 2014 23:11:59 +0800 Subject: [PATCH] use new direct access on endpoints --- migen/actorlib/crc.py | 10 +++++----- migen/actorlib/dma_lasmi.py | 8 ++++---- migen/actorlib/dma_wishbone.py | 8 ++++---- migen/actorlib/fifo.py | 4 ++-- migen/actorlib/misc.py | 8 ++++---- migen/actorlib/spi.py | 8 ++++---- 6 files changed, 23 insertions(+), 23 deletions(-) diff --git a/migen/actorlib/crc.py b/migen/actorlib/crc.py index 58097a6a..74139c94 100644 --- a/migen/actorlib/crc.py +++ b/migen/actorlib/crc.py @@ -29,7 +29,7 @@ class CRCInserter(Module): ### - dw = flen(self.sink.payload.d) + dw = flen(self.sink.d) self.submodules.crc = crc_class(dw) self.submodules.fsm = fsm = FSM(reset_state="IDLE") @@ -43,7 +43,7 @@ class CRCInserter(Module): ) fsm.act("COPY", self.crc.ce.eq(self.sink.stb & self.source.ack), - self.crc.d.eq(self.sink.payload.d), + self.crc.d.eq(self.sink.d), Record.connect(self.sink, self.source), self.source.eop.eq(0), If(self.sink.stb & self.sink.eop & self.source.ack, @@ -55,7 +55,7 @@ class CRCInserter(Module): cnt_done = Signal() fsm.act("INSERT", self.source.stb.eq(1), - chooser(self.crc.value, cnt, self.source.payload.d, reverse=True), + chooser(self.crc.value, cnt, self.source.d, reverse=True), If(cnt_done, self.source.eop.eq(1), If(self.source.ack, NextState("IDLE")) @@ -99,7 +99,7 @@ class CRCChecker(Module): ### - dw = flen(self.sink.payload.d) + dw = flen(self.sink.d) self.submodules.crc = crc_class(dw) fsm = FSM(reset_state="IDLE") @@ -116,7 +116,7 @@ class CRCChecker(Module): fsm.act("COPY", Record.connect(self.sink, self.source), self.crc.ce.eq(self.sink.stb & (self.sink.ack | self.sink.eop)), - self.crc.d.eq(self.sink.payload.d), + self.crc.d.eq(self.sink.d), If(self.sink.stb & self.sink.eop, self.sink.ack.eq(0), self.source.stb.eq(0), diff --git a/migen/actorlib/dma_lasmi.py b/migen/actorlib/dma_lasmi.py index 8f837d99..38da442b 100644 --- a/migen/actorlib/dma_lasmi.py +++ b/migen/actorlib/dma_lasmi.py @@ -20,7 +20,7 @@ class Reader(Module): self.comb += [ lasmim.we.eq(0), lasmim.stb.eq(self.address.stb & request_enable), - lasmim.adr.eq(self.address.payload.a), + lasmim.adr.eq(self.address.a), self.address.ack.eq(lasmim.req_ack & request_enable), request_issued.eq(lasmim.stb & lasmim.req_ack) ] @@ -59,7 +59,7 @@ class Reader(Module): self.data.stb.eq(fifo.readable), fifo.re.eq(self.data.ack), - self.data.payload.d.eq(fifo.dout), + self.data.d.eq(fifo.dout), data_dequeued.eq(self.data.stb & self.data.ack) ] @@ -80,10 +80,10 @@ class Writer(Module): self.comb += [ lasmim.we.eq(1), lasmim.stb.eq(fifo.writable & self.address_data.stb), - lasmim.adr.eq(self.address_data.payload.a), + lasmim.adr.eq(self.address_data.a), self.address_data.ack.eq(fifo.writable & lasmim.req_ack), fifo.we.eq(self.address_data.stb & lasmim.req_ack), - fifo.din.eq(self.address_data.payload.d) + fifo.din.eq(self.address_data.d) ] data_valid = lasmim.dat_ack diff --git a/migen/actorlib/dma_wishbone.py b/migen/actorlib/dma_wishbone.py index 785038f6..66063627 100644 --- a/migen/actorlib/dma_wishbone.py +++ b/migen/actorlib/dma_wishbone.py @@ -21,10 +21,10 @@ class Reader(Module): bus_stb.eq(self.address.stb & (~data_reg_loaded | self.data.ack)), self.bus.cyc.eq(bus_stb), self.bus.stb.eq(bus_stb), - self.bus.adr.eq(self.address.payload.a), + self.bus.adr.eq(self.address.a), self.address.ack.eq(self.bus.ack), self.data.stb.eq(data_reg_loaded), - self.data.payload.d.eq(data_reg) + self.data.d.eq(data_reg) ] self.sync += [ If(self.data.ack, data_reg_loaded.eq(0)), @@ -47,8 +47,8 @@ class Writer(Module): self.bus.we.eq(1), self.bus.cyc.eq(self.address_data.stb), self.bus.stb.eq(self.address_data.stb), - self.bus.adr.eq(self.address_data.payload.a), + self.bus.adr.eq(self.address_data.a), self.bus.sel.eq(0xf), - self.bus.dat_w.eq(self.address_data.payload.d), + self.bus.dat_w.eq(self.address_data.d), self.address_data.ack.eq(self.bus.ack) ] diff --git a/migen/actorlib/fifo.py b/migen/actorlib/fifo.py index 78be8200..0705016a 100644 --- a/migen/actorlib/fifo.py +++ b/migen/actorlib/fifo.py @@ -18,7 +18,7 @@ class _FIFOActor(Module): self.fifo.din.eq(self.sink.payload), self.source.stb.eq(self.fifo.readable), - self.source.payload.eq(self.fifo.dout), + self.source.eq(self.fifo.dout), self.fifo.re.eq(self.source.ack) ] @@ -28,4 +28,4 @@ class SyncFIFO(_FIFOActor): class AsyncFIFO(_FIFOActor): def __init__(self, layout, depth): - _FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth) + _FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth) diff --git a/migen/actorlib/misc.py b/migen/actorlib/misc.py index 3c0546da..302216c9 100644 --- a/migen/actorlib/misc.py +++ b/migen/actorlib/misc.py @@ -32,8 +32,8 @@ class IntSequence(Module): self.sync += [ If(load, counter.eq(0), - maximum.eq(self.parameters.payload.maximum), - offset.eq(self.parameters.payload.offset) if offsetbits else None + maximum.eq(self.parameters.maximum), + offset.eq(self.parameters.offset) if offsetbits else None ).Elif(ce, If(last, counter.eq(0) @@ -43,9 +43,9 @@ class IntSequence(Module): ) ] if offsetbits: - self.comb += self.source.payload.value.eq(counter + offset) + self.comb += self.source.value.eq(counter + offset) else: - self.comb += self.source.payload.value.eq(counter) + self.comb += self.source.value.eq(counter) fsm = FSM() self.submodules += fsm diff --git a/migen/actorlib/spi.py b/migen/actorlib/spi.py index 490102ec..eff515e6 100644 --- a/migen/actorlib/spi.py +++ b/migen/actorlib/spi.py @@ -128,8 +128,8 @@ class _DMAController(Module): class DMAReadController(_DMAController): def __init__(self, bus_accessor, *args, **kwargs): - bus_aw = flen(bus_accessor.address.payload.a) - bus_dw = flen(bus_accessor.data.payload.d) + bus_aw = flen(bus_accessor.address.a) + bus_dw = flen(bus_accessor.data.d) _DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs) g = DataFlowGraph() @@ -147,8 +147,8 @@ class DMAReadController(_DMAController): class DMAWriteController(_DMAController): def __init__(self, bus_accessor, *args, ack_when_inactive=False, **kwargs): - bus_aw = flen(bus_accessor.address_data.payload.a) - bus_dw = flen(bus_accessor.address_data.payload.d) + bus_aw = flen(bus_accessor.address_data.a) + bus_dw = flen(bus_accessor.address_data.d) _DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs) g = DataFlowGraph() -- 2.30.2