From 07f7c13f494dec2c75584ccef72540bc107a2d68 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 29 Nov 2023 19:41:22 +0000 Subject: [PATCH] comments --- src/openpower/decoder/isa/test_caller_svp64_pospopcount.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py index d13ea570..efc31ef5 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py +++ b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py @@ -45,10 +45,10 @@ class PosPopCountTestCase(FHDLTestCase): "sv.lbzu/pi/dw=8 *6, 1(4)", # should be /lf here as well # gather performs the transpose (which gets us to positional..) "gbbd 8,6", - # now those bits have been turned around, + # now those bits have been turned around, popcount and sum them "setvl 0,0,8,0,1,1", # set MVL=VL=8 "sv.popcntd/sw=8 *24,*8", # do the (now transposed) popcount - "sv.add *16,*16,*24", + "sv.add *16,*16,*24", # and accumulate in results # branch back if still CTR "sv.bc/all 16, *0, -0x28", # CTR mode, reduce VL by CTR ] -- 2.30.2