From 080afdc3f9db811d7b53dd0da33d122219c594fd Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 26 Jun 2013 22:45:47 +0200 Subject: [PATCH] fhdl/verilog: fix signedness rules for comparison --- migen/fhdl/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 8dc404fe..d9683e94 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -51,7 +51,7 @@ def _printexpr(ns, node): s = s1 elif arity == 2: r2, s2 = _printexpr(ns, node.operands[1]) - if node.op in ["+", "-", "*", "&", "^", "|"]: + if node.op not in ["<<<", ">>>"]: if s2 and not s1: r1 = "$signed({1'd0, " + r1 + "})" if s1 and not s2: -- 2.30.2