From 081d9318bcf1ee13549ddcb0983cba5f00b4272c Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 1 Jan 2020 08:27:47 +0000 Subject: [PATCH] ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires). --- techlibs/ecp5/brams.txt | 62 ++++++++ techlibs/ecp5/lutrams.txt | 9 ++ tests/arch/common/blockrom.v | 10 +- tests/arch/ecp5/memories.ys | 284 +++++++++++++++++++++++++++++++++++ tests/arch/ice40/memories.ys | 16 ++ 5 files changed, 376 insertions(+), 5 deletions(-) create mode 100644 tests/arch/ecp5/memories.ys diff --git a/techlibs/ecp5/brams.txt b/techlibs/ecp5/brams.txt index 777ccaa2e..d34d9ec07 100644 --- a/techlibs/ecp5/brams.txt +++ b/techlibs/ecp5/brams.txt @@ -37,7 +37,17 @@ bram $__ECP5_DP16KD clkpol 2 3 endbram +# The syn_* attributes are described in: +# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx +attr_icase 1 + match $__ECP5_PDPW16KD + # implicitly requested RAM or ROM + attribute !syn_ramstyle syn_ramstyle=auto + attribute !syn_romstyle syn_romstyle=auto + attribute !ram_block + attribute !rom_block + attribute !logic_block min bits 2048 min efficiency 5 shuffle_enable A @@ -45,8 +55,60 @@ match $__ECP5_PDPW16KD or_next_if_better endmatch +match $__ECP5_PDPW16KD + # explicitly requested RAM + attribute syn_ramstyle=block_ram ram_block + attribute !syn_romstyle + attribute !rom_block + attribute !logic_block + min wports 1 + shuffle_enable A + make_transp + or_next_if_better +endmatch + +match $__ECP5_PDPW16KD + # explicitly requested ROM + attribute syn_romstyle=ebr rom_block + attribute !syn_ramstyle + attribute !ram_block + attribute !logic_block + max wports 0 + shuffle_enable A + make_transp + or_next_if_better +endmatch + match $__ECP5_DP16KD + # implicitly requested RAM or ROM + attribute !syn_ramstyle syn_ramstyle=auto + attribute !syn_romstyle syn_romstyle=auto + attribute !ram_block + attribute !rom_block + attribute !logic_block min bits 2048 min efficiency 5 shuffle_enable A + or_next_if_better +endmatch + +match $__ECP5_DP16KD + # explicitly requested RAM + attribute syn_ramstyle=block_ram ram_block + attribute !syn_romstyle + attribute !rom_block + attribute !logic_block + min wports 1 + shuffle_enable A + or_next_if_better +endmatch + +match $__ECP5_DP16KD + # explicitly requested ROM + attribute syn_romstyle=ebr rom_block + attribute !syn_ramstyle + attribute !ram_block + attribute !logic_block + max wports 0 + shuffle_enable A endmatch diff --git a/techlibs/ecp5/lutrams.txt b/techlibs/ecp5/lutrams.txt index b94357429..9e6a23eba 100644 --- a/techlibs/ecp5/lutrams.txt +++ b/techlibs/ecp5/lutrams.txt @@ -11,7 +11,16 @@ bram $__TRELLIS_DPR16X4 clkpol 0 2 endbram +# The syn_* attributes are described in: +# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx +attr_icase 1 + match $__TRELLIS_DPR16X4 + attribute !syn_ramstyle syn_ramstyle=auto syn_ramstyle=distributed + attribute !syn_romstyle syn_romstyle=auto + attribute !ram_block + attribute !rom_block + attribute !logic_block make_outreg min wports 1 endmatch diff --git a/tests/arch/common/blockrom.v b/tests/arch/common/blockrom.v index 6f6c9d946..93f5c9ddf 100644 --- a/tests/arch/common/blockrom.v +++ b/tests/arch/common/blockrom.v @@ -10,16 +10,16 @@ module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) reg [WORD:0] data_out_r; reg [WORD:0] memory [0:DEPTH]; - integer i,j = 16'hACE1; + integer i,j = 64'hF4B1CA8127865242; initial for (i = 0; i <= DEPTH; i++) begin // In case this ROM will be implemented in fabric: fill the memory with some data // uncorrelated with the address, or Yosys might see through the ruse and e.g. not // emit any LUTs at all for `memory[i] = i;`, just a latch. - memory[i] = j; - j = j ^ (j >> 7); - j = j ^ (j << 9); - j = j ^ (j >> 13); + memory[i] = j * 64'h2545F4914F6CDD1D; + j = j ^ (j >> 12); + j = j ^ (j << 25); + j = j ^ (j >> 27); end always @(posedge clk) begin diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys new file mode 100644 index 000000000..64005ba0b --- /dev/null +++ b/tests/arch/ecp5/memories.ys @@ -0,0 +1,284 @@ +# ================================ RAM ================================ +# RAM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:PDPW16KD + +## With parameters + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:PDPW16KD # too inefficient +select -assert-count 9 t:TRELLIS_DPR16X4 + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +setattr -set syn_ramstyle "block_ram" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:PDPW16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +setattr -set syn_ramstyle "Block_RAM" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:PDPW16KD # any case works + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +setattr -set ram_block 1 m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:PDPW16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +setattr -set syn_ramstyle "registers" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly +select -assert-count 180 t:TRELLIS_FF + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +setattr -set logic_block 1 m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly +select -assert-count 180 t:TRELLIS_FF + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +setattr -set syn_romstyle "ebr" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:PDPW16KD # requested BROM but this is a RAM +select -assert-count 180 t:TRELLIS_FF + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +setattr -set rom_block 1 m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:PDPW16KD # requested BROM but this is a RAM +select -assert-count 180 t:TRELLIS_FF + +# RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:DP16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 9 sync_ram_sdp +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:DP16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 4 sync_ram_sdp +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:DP16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 13 -set DATA_WIDTH 2 sync_ram_sdp +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:DP16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:DP16KD + +## With parameters + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:DP16KD # too inefficient +select -assert-count 5 t:TRELLIS_DPR16X4 + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +setattr -set syn_ramstyle "block_ram" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:DP16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +setattr -set syn_ramstyle "Block_RAM" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:DP16KD # any case works + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +setattr -set ram_block 1 m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:DP16KD + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +setattr -set syn_ramstyle "registers" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:DP16KD # requested FFRAM explicitly +select -assert-count 90 t:TRELLIS_FF + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +setattr -set logic_block 1 m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:DP16KD # requested FFRAM explicitly +select -assert-count 90 t:TRELLIS_FF + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +setattr -set syn_romstyle "ebr" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:DP16KD # requested BROM but this is a RAM +select -assert-count 90 t:TRELLIS_FF + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +setattr -set rom_block 1 m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:DP16KD # requested BROM but this is a RAM +select -assert-count 90 t:TRELLIS_FF + +# RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4 + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:TRELLIS_DPR16X4 + +## With parameters + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp +setattr -set syn_ramstyle "distributed" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:TRELLIS_DPR16X4 + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp +setattr -set syn_ramstyle "registers" m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly +select -assert-count 68 t:TRELLIS_FF + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp +setattr -set logic_block 1 m:memory +synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly +select -assert-count 68 t:TRELLIS_FF + +# ================================ ROM ================================ +# ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_rom +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 1 t:PDPW16KD + +## With parameters + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom +write_ilang +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:PDPW16KD # too inefficient +select -assert-min 18 t:LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +setattr -set syn_romstyle "ebr" m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 1 t:PDPW16KD + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +setattr -set rom_block 1 m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 1 t:PDPW16KD + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom +setattr -set syn_romstyle "logic" m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly +select -assert-min 18 t:LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom +setattr -set logic_block 1 m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly +select -assert-min 18 t:LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +setattr -set syn_ramstyle "block_ram" m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:PDPW16KD # requested BRAM but this is a ROM +select -assert-min 18 t:LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +setattr -set ram_block 1 m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:PDPW16KD # requested BRAM but this is a ROM +select -assert-min 18 t:LUT4 + +# ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_rom +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 1 t:DP16KD + +## With parameters + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom +write_ilang +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:DP16KD # too inefficient +select -assert-min 9 t:LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +setattr -set syn_romstyle "ebr" m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 1 t:DP16KD + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +setattr -set rom_block 1 m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 1 t:DP16KD + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom +setattr -set syn_romstyle "logic" m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:DP16KD # requested LUTROM explicitly +select -assert-min 9 t:LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom +setattr -set logic_block 1 m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:DP16KD # requested LUTROM explicitly +select -assert-min 9 t:LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +setattr -set syn_ramstyle "block_ram" m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:DP16KD # requested BRAM but this is a ROM +select -assert-min 9 t:LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +setattr -set ram_block 1 m:memory +synth_ecp5 -top sync_rom; cd sync_rom +select -assert-count 0 t:DP16KD # requested BRAM but this is a ROM +select -assert-min 9 t:LUT4 diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index 43bcf2452..86a60b258 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -1,3 +1,4 @@ +# ================================ RAM ================================ # RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K design -reset; read_verilog ../common/blockram.v @@ -46,6 +47,13 @@ setattr -set ram_block 1 m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_ramstyle "registers" m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly +select -assert-min 1 t:SB_DFFE + design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set logic_block 1 m:memory @@ -67,6 +75,7 @@ synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM select -assert-min 1 t:SB_DFFE +# ================================ ROM ================================ # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K design -reset; read_verilog ../common/blockrom.v @@ -110,6 +119,13 @@ setattr -set rom_block 1 m:memory synth_ice40 -top sync_rom; cd sync_rom select -assert-count 1 t:SB_RAM40_4K +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set syn_romstyle "logic" m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly +select -assert-min 1 t:SB_LUT4 + design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set logic_block 1 m:memory -- 2.30.2