From 082b03016c616a5233ee00e7dd3f88de18b8acd7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 25 Sep 2018 09:31:30 +0200 Subject: [PATCH] targets: use new clock abstraction on all 7-series targets --- litex/boards/targets/genesys2.py | 62 +++++--------------------- litex/boards/targets/kc705.py | 62 +++++--------------------- litex/boards/targets/nexys4ddr.py | 69 ++++++----------------------- litex/boards/targets/nexys_video.py | 69 ++++++----------------------- 4 files changed, 48 insertions(+), 214 deletions(-) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 68431922..91df0d38 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -3,10 +3,10 @@ import argparse from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import genesys2 +from litex.soc.cores.clock import * from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -19,59 +19,19 @@ from liteeth.core.mac import LiteEthMAC class _CRG(Module): - def __init__(self, platform): + def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() - clk200 = platform.request("clk200") - clk200_se = Signal() - self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se) - - rst_n = platform.request("cpu_reset_n") - - pll_locked = Signal() - pll_fb = Signal() - pll_sys = Signal() - pll_sys4x = Signal() - pll_clk200 = Signal() - self.specials += [ - Instance("PLLE2_BASE", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - - # VCO @ 1GHz - p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0, - p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, - i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, - - # 125MHz - p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=pll_sys, - - # 500MHz - p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=pll_sys4x, - - # 200MHz - p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, - o_CLKOUT2=pll_clk200 - ), - Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), - Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst_n), - AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | ~rst_n), - ] - - reset_counter = Signal(4, reset=15) - ic_reset = Signal(reset=1) - self.sync.clk200 += \ - If(reset_counter != 0, - reset_counter.eq(reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) + self.submodules.pll = pll = S7MMCM() + self.comb += pll.reset.eq(~platform.request("cpu_reset_n")) + pll.register_clkin(platform.request("clk200"), 200e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_clk200, 200e6) + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) class BaseSoC(SoCSDRAM): @@ -87,7 +47,7 @@ class BaseSoC(SoCSDRAM): integrated_sram_size=0x8000, **kwargs) - self.submodules.crg = _CRG(platform) + self.submodules.crg = _CRG(platform, sys_clk_freq) # sdram self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index bbe42d8d..10078b30 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -3,10 +3,10 @@ import argparse from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import kc705 +from litex.soc.cores.clock import * from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -19,59 +19,19 @@ from liteeth.core.mac import LiteEthMAC class _CRG(Module): - def __init__(self, platform): + def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() - clk200 = platform.request("clk200") - clk200_se = Signal() - self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se) - - rst = platform.request("cpu_reset") - - pll_locked = Signal() - pll_fb = Signal() - pll_sys = Signal() - pll_sys4x = Signal() - pll_clk200 = Signal() - self.specials += [ - Instance("PLLE2_BASE", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - - # VCO @ 1GHz - p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0, - p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, - i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, - - # 125MHz - p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=pll_sys, - - # 500MHz - p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=pll_sys4x, - - # 200MHz - p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, - o_CLKOUT2=pll_clk200 - ), - Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), - Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst), - AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst), - ] - - reset_counter = Signal(4, reset=15) - ic_reset = Signal(reset=1) - self.sync.clk200 += \ - If(reset_counter != 0, - reset_counter.eq(reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) + self.submodules.pll = pll = S7MMCM() + self.comb += pll.reset.eq(platform.request("cpu_reset")) + pll.register_clkin(platform.request("clk200"), 200e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_clk200, 200e6) + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) class BaseSoC(SoCSDRAM): @@ -87,7 +47,7 @@ class BaseSoC(SoCSDRAM): integrated_sram_size=0x8000, **kwargs) - self.submodules.crg = _CRG(platform) + self.submodules.crg = _CRG(platform, sys_clk_freq) # sdram self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index f65c5d7f..fb863e71 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -3,10 +3,10 @@ import argparse from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import nexys4ddr +from litex.soc.cores.clock import * from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -16,66 +16,23 @@ from litedram.phy import s7ddrphy class _CRG(Module): - def __init__(self, platform): + def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() - clk100 = platform.request("clk100") - rst = ~platform.request("cpu_reset") - - pll_locked = Signal() - pll_fb = Signal() - pll_sys = Signal() - pll_sys2x = Signal() - pll_sys2x_dqs = Signal() - pll_clk200 = Signal() - self.specials += [ - Instance("PLLE2_BASE", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - - # VCO @ 1600 MHz - p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0, - p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1, - i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, - - # 100 MHz - p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=pll_sys, - - # 200 MHz - p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=pll_sys2x, - - # 200 MHz dqs - p_CLKOUT2_DIVIDE=8, p_CLKOUT2_PHASE=90.0, - o_CLKOUT2=pll_sys2x_dqs, - - # 200 MHz - p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0, - o_CLKOUT3=pll_clk200 - ), - Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=pll_sys2x, o_O=self.cd_sys2x.clk), - Instance("BUFG", i_I=pll_sys2x_dqs, o_O=self.cd_sys2x_dqs.clk), - Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), - Instance("BUFG", i_I=clk100, o_O=self.cd_clk100.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst), - AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst), - AsyncResetSynchronizer(self.cd_clk100, ~pll_locked | rst), - ] - - reset_counter = Signal(4, reset=15) - ic_reset = Signal(reset=1) - self.sync.clk200 += \ - If(reset_counter != 0, - reset_counter.eq(reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) + self.submodules.pll = pll = S7MMCM() + self.comb += pll.reset.eq(~platform.request("cpu_reset")) + pll.register_clkin(platform.request("clk100"), 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_clk100, 100e6) + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) class BaseSoC(SoCSDRAM): @@ -91,7 +48,7 @@ class BaseSoC(SoCSDRAM): integrated_sram_size=0x8000, **kwargs) - self.submodules.crg = _CRG(platform) + self.submodules.crg = _CRG(platform, sys_clk_freq) # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 8e9acaf4..9ce1719d 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -3,10 +3,10 @@ import argparse from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import nexys_video +from litex.soc.cores.clock import * from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -19,66 +19,23 @@ from liteeth.core.mac import LiteEthMAC class _CRG(Module): - def __init__(self, platform): + def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() - clk100 = platform.request("clk100") - rst = ~platform.request("cpu_reset") - - pll_locked = Signal() - pll_fb = Signal() - pll_sys = Signal() - pll_sys4x = Signal() - pll_sys4x_dqs = Signal() - pll_clk200 = Signal() - self.specials += [ - Instance("PLLE2_BASE", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - - # VCO @ 1600 MHz - p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0, - p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1, - i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, - - # 100 MHz - p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=pll_sys, - - # 400 MHz - p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=pll_sys4x, - - # 400 MHz dqs - p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0, - o_CLKOUT2=pll_sys4x_dqs, - - # 200 MHz - p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0, - o_CLKOUT3=pll_clk200 - ), - Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), - Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk), - Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), - Instance("BUFG", i_I=clk100, o_O=self.cd_clk100.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst), - AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst), - AsyncResetSynchronizer(self.cd_clk100, ~pll_locked | rst), - ] - - reset_counter = Signal(4, reset=15) - ic_reset = Signal(reset=1) - self.sync.clk200 += \ - If(reset_counter != 0, - reset_counter.eq(reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) + self.submodules.pll = pll = S7MMCM() + self.comb += pll.reset.eq(~platform.request("cpu_reset")) + pll.register_clkin(platform.request("clk100"), 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_clk100, 100e6) + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) class BaseSoC(SoCSDRAM): @@ -94,7 +51,7 @@ class BaseSoC(SoCSDRAM): integrated_sram_size=0x8000, **kwargs) - self.submodules.crg = _CRG(platform) + self.submodules.crg = _CRG(platform, sys_clk_freq) # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) -- 2.30.2