From 08322bb3cc907fb32ec995eff3036949507ee335 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 23 Jul 2019 22:33:10 +0100 Subject: [PATCH] more comments --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index 13321698..adc68ffc 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -398,12 +398,16 @@ class DivPipeCoreCalculateStage(Elaboratable): m.d.comb += t.compare_rhs.eq(self.i.compare_rhs) m.d.comb += t.operation.eq(self.i.operation) + # get the trial output trial_compare_rhs_values.append(t.trial_compare_rhs) + # make the trial comparison against the [invariant] lhs. + # trial_compare_rhs is always decreasing as trial_bits increases pass_flag = Signal(name=f"pass_flag_{trial_bits}", reset_less=True) m.d.comb += pass_flag.eq(self.i.compare_lhs >= t.trial_compare_rhs) pfl.append(pass_flag) + # Cat all the pass flags list together (easier to handle, below) pass_flags = Signal(radix, reset_less=True) m.d.comb += pass_flags.eq(Cat(*pfl)) -- 2.30.2