From 0851580aada37c8e1b1d2b695100fbcfaf4e0946 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 7 Feb 2011 19:23:13 -0800
Subject: [PATCH] Stats: Re update stats.

---
 .../ref/alpha/tru64/o3-timing/config.ini      |  11 +-
 .../00.gzip/ref/alpha/tru64/o3-timing/simout  |   8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  31 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-atomic/simerr      |   6 +
 .../ref/alpha/tru64/simple-atomic/simout      |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |  26 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-timing/simerr      |   6 +
 .../ref/alpha/tru64/simple-timing/simout      |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  26 +-
 .../ref/arm/linux/o3-timing/config.ini        |  13 +-
 .../00.gzip/ref/arm/linux/o3-timing/simout    |   8 +-
 .../00.gzip/ref/arm/linux/o3-timing/stats.txt |  30 +-
 .../ref/arm/linux/simple-atomic/config.ini    |  15 +-
 .../ref/arm/linux/simple-atomic/simout        |  10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/arm/linux/simple-timing/config.ini    |  15 +-
 .../ref/arm/linux/simple-timing/simerr        |   4 +
 .../ref/arm/linux/simple-timing/simout        |  10 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  26 +-
 .../ref/sparc/linux/o3-timing/config.ini      |  11 +-
 .../00.gzip/ref/sparc/linux/o3-timing/simout  |   8 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |  31 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |  13 +-
 .../ref/sparc/linux/simple-atomic/simout      |   8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |  26 +-
 .../ref/sparc/linux/simple-timing/config.ini  |  15 +-
 .../ref/sparc/linux/simple-timing/simout      |  10 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  26 +-
 .../ref/x86/linux/o3-timing/config.ini        |   9 +-
 .../00.gzip/ref/x86/linux/o3-timing/simout    |   8 +-
 .../00.gzip/ref/x86/linux/o3-timing/stats.txt |  29 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   9 +-
 .../ref/x86/linux/simple-atomic/simout        |   8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/x86/linux/simple-timing/config.ini    |   9 +-
 .../ref/x86/linux/simple-timing/simout        |   8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  26 +-
 .../alpha/linux/tsunami-o3-dual/config.ini    |  11 +-
 .../ref/alpha/linux/tsunami-o3-dual/simout    |   8 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt |  54 +-
 .../ref/alpha/linux/tsunami-o3/config.ini     |  11 +-
 .../ref/alpha/linux/tsunami-o3/simout         |   8 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt      |  31 +-
 .../10.mcf/ref/arm/linux/o3-timing/config.ini |  15 +-
 .../10.mcf/ref/arm/linux/o3-timing/simout     |   8 +-
 .../10.mcf/ref/arm/linux/o3-timing/stats.txt  |  31 +-
 .../ref/arm/linux/simple-atomic/config.ini    |  17 +-
 .../10.mcf/ref/arm/linux/simple-atomic/simout |  10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/arm/linux/simple-timing/config.ini    |  17 +-
 .../10.mcf/ref/arm/linux/simple-timing/simerr |   4 +
 .../10.mcf/ref/arm/linux/simple-timing/simout |  10 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  26 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |  15 +-
 .../ref/sparc/linux/simple-atomic/simout      |   8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |  26 +-
 .../ref/sparc/linux/simple-timing/config.ini  |  17 +-
 .../ref/sparc/linux/simple-timing/simout      |  10 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  26 +-
 .../10.mcf/ref/x86/linux/o3-timing/config.ini |   9 +-
 .../10.mcf/ref/x86/linux/o3-timing/simout     |   8 +-
 .../10.mcf/ref/x86/linux/o3-timing/stats.txt  |  30 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   9 +-
 .../10.mcf/ref/x86/linux/simple-atomic/simout |   8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/x86/linux/simple-timing/config.ini    |   9 +-
 .../10.mcf/ref/x86/linux/simple-timing/simout |   8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  26 +-
 .../ref/arm/linux/o3-timing/config.ini        |  15 +-
 .../20.parser/ref/arm/linux/o3-timing/simout  |   8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  30 +-
 .../ref/arm/linux/simple-atomic/config.ini    |  17 +-
 .../ref/arm/linux/simple-atomic/simout        |  10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/arm/linux/simple-timing/config.ini    |  17 +-
 .../ref/arm/linux/simple-timing/simerr        |   2 +
 .../ref/arm/linux/simple-timing/simout        |  10 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  26 +-
 .../ref/x86/linux/o3-timing/config.ini        |   9 +-
 .../20.parser/ref/x86/linux/o3-timing/simout  |   8 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  29 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   9 +-
 .../ref/x86/linux/simple-atomic/simout        |   8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/x86/linux/simple-timing/config.ini    |   9 +-
 .../ref/x86/linux/simple-timing/simout        |   8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  26 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |  11 +-
 .../30.eon/ref/alpha/tru64/o3-timing/simout   |   8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  31 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-atomic/simerr      |   6 +
 .../ref/alpha/tru64/simple-atomic/simout      |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |  26 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-timing/simerr      |   6 +
 .../ref/alpha/tru64/simple-timing/simout      |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  26 +-
 .../30.eon/ref/arm/linux/o3-timing/config.ini |  13 +-
 .../30.eon/ref/arm/linux/o3-timing/simout     |   8 +-
 .../30.eon/ref/arm/linux/o3-timing/stats.txt  |  31 +-
 .../ref/arm/linux/simple-atomic/config.ini    |  15 +-
 .../30.eon/ref/arm/linux/simple-atomic/simout |  10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/arm/linux/simple-timing/config.ini    |  15 +-
 .../30.eon/ref/arm/linux/simple-timing/simerr |  10 +-
 .../30.eon/ref/arm/linux/simple-timing/simout |  10 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  26 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |  11 +-
 .../ref/alpha/tru64/o3-timing/simout          |   8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  31 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-atomic/simerr      |   6 +
 .../ref/alpha/tru64/simple-atomic/simout      |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |  26 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-timing/simerr      |   6 +
 .../ref/alpha/tru64/simple-timing/simout      |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  26 +-
 .../ref/arm/linux/o3-timing/config.ini        |  13 +-
 .../40.perlbmk/ref/arm/linux/o3-timing/simout |   8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  31 +-
 .../ref/arm/linux/simple-atomic/config.ini    |  15 +-
 .../ref/arm/linux/simple-atomic/simout        |  10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/arm/linux/simple-timing/config.ini    |  15 +-
 .../ref/arm/linux/simple-timing/simerr        |   6 +
 .../ref/arm/linux/simple-timing/simout        |  10 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  26 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |  11 +-
 .../ref/alpha/tru64/inorder-timing/simout     |   8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  10 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |  11 +-
 .../ref/alpha/tru64/o3-timing/simout          |   8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  31 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-atomic/simerr      |   6 +
 .../ref/alpha/tru64/simple-atomic/simout      |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |  26 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-timing/simerr      |   6 +
 .../ref/alpha/tru64/simple-timing/simout      |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  26 +-
 .../ref/arm/linux/o3-timing/config.ini        |  13 +-
 .../50.vortex/ref/arm/linux/o3-timing/simout  |  10 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  31 +-
 .../ref/arm/linux/simple-atomic/config.ini    |  15 +-
 .../ref/arm/linux/simple-atomic/simout        |  10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/arm/linux/simple-timing/config.ini    |  15 +-
 .../ref/arm/linux/simple-timing/simerr        |   8 +
 .../ref/arm/linux/simple-timing/simout        |  10 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  26 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |  13 +-
 .../ref/sparc/linux/simple-atomic/simout      |   8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |  26 +-
 .../ref/sparc/linux/simple-timing/config.ini  |  15 +-
 .../ref/sparc/linux/simple-timing/simout      |  10 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  26 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |  11 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/simout |   8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  31 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-atomic/simerr      |   6 +
 .../ref/alpha/tru64/simple-atomic/simout      |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |  26 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-timing/simerr      |   6 +
 .../ref/alpha/tru64/simple-timing/simout      |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  26 +-
 .../ref/arm/linux/o3-timing/config.ini        |  13 +-
 .../60.bzip2/ref/arm/linux/o3-timing/simout   |   8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  31 +-
 .../ref/arm/linux/simple-atomic/config.ini    |  15 +-
 .../ref/arm/linux/simple-atomic/simout        |  10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/arm/linux/simple-timing/config.ini    |  15 +-
 .../ref/arm/linux/simple-timing/simerr        |   2 +
 .../ref/arm/linux/simple-timing/simout        |  10 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  26 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   9 +-
 .../ref/x86/linux/simple-atomic/simout        |   8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/x86/linux/simple-timing/config.ini    |   9 +-
 .../ref/x86/linux/simple-timing/simout        |   8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  26 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |  11 +-
 .../ref/alpha/tru64/inorder-timing/simout     |   8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  10 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |  11 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/simout |  10 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  31 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-atomic/simerr      |   6 +
 .../ref/alpha/tru64/simple-atomic/simout      |  12 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |  26 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-timing/simerr      |   6 +
 .../ref/alpha/tru64/simple-timing/simout      |  12 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  26 +-
 .../ref/arm/linux/o3-timing/config.ini        |  13 +-
 .../70.twolf/ref/arm/linux/o3-timing/simout   |   8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  31 +-
 .../ref/arm/linux/simple-atomic/config.ini    |  15 +-
 .../ref/arm/linux/simple-atomic/simout        |  14 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/arm/linux/simple-timing/config.ini    |  15 +-
 .../ref/arm/linux/simple-timing/simerr        |  10 +
 .../ref/arm/linux/simple-timing/simout        |  14 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  26 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |  13 +-
 .../ref/sparc/linux/simple-atomic/simout      |  10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |  26 +-
 .../ref/sparc/linux/simple-timing/config.ini  |  13 +-
 .../ref/sparc/linux/simple-timing/simout      |  16 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  26 +-
 .../ref/x86/linux/o3-timing/config.ini        |   9 +-
 .../70.twolf/ref/x86/linux/o3-timing/simout   |  12 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  31 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   9 +-
 .../ref/x86/linux/simple-atomic/simout        |  12 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/x86/linux/simple-timing/config.ini    |   9 +-
 .../ref/x86/linux/simple-timing/simout        |  12 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  26 +-
 .../solaris/t1000-simple-atomic/config.ini    |  26 +-
 .../sparc/solaris/t1000-simple-atomic/simout  |   8 +-
 .../solaris/t1000-simple-atomic/stats.txt     |  26 +-
 .../ref/alpha/linux/inorder-timing/config.ini |  13 +-
 .../ref/alpha/linux/inorder-timing/simout     |   8 +-
 .../ref/alpha/linux/inorder-timing/stats.txt  |  10 +-
 .../ref/alpha/linux/o3-timing/config.ini      |  11 +-
 .../00.hello/ref/alpha/linux/o3-timing/simout |   8 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |  31 +-
 .../ref/alpha/linux/simple-atomic/config.ini  |  13 +-
 .../ref/alpha/linux/simple-atomic/simout      |   8 +-
 .../ref/alpha/linux/simple-atomic/stats.txt   |  24 +-
 .../alpha/linux/simple-timing-ruby/config.ini | 186 +++----
 .../alpha/linux/simple-timing-ruby/ruby.stats | 302 ++++++------
 .../ref/alpha/linux/simple-timing-ruby/simout |   8 +-
 .../alpha/linux/simple-timing-ruby/stats.txt  |  26 +-
 .../ref/alpha/linux/simple-timing/config.ini  |  11 +-
 .../ref/alpha/linux/simple-timing/simout      |  12 +-
 .../ref/alpha/linux/simple-timing/stats.txt   |  24 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |  11 +-
 .../00.hello/ref/alpha/tru64/o3-timing/simout |   8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  30 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |  13 +-
 .../ref/alpha/tru64/simple-atomic/simout      |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |  26 +-
 .../alpha/tru64/simple-timing-ruby/config.ini | 186 +++----
 .../alpha/tru64/simple-timing-ruby/ruby.stats | 310 ++++++------
 .../ref/alpha/tru64/simple-timing-ruby/simout |   8 +-
 .../alpha/tru64/simple-timing-ruby/stats.txt  |  26 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |  11 +-
 .../ref/alpha/tru64/simple-timing/simout      |  12 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  26 +-
 .../ref/arm/linux/o3-timing/config.ini        |  13 +-
 .../00.hello/ref/arm/linux/o3-timing/simout   |   8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  30 +-
 .../ref/arm/linux/simple-atomic/config.ini    |  13 +-
 .../ref/arm/linux/simple-atomic/simout        |  10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |  26 +-
 .../ref/arm/linux/simple-timing/config.ini    |  13 +-
 .../ref/arm/linux/simple-timing/simout        |   8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  24 +-
 .../ref/mips/linux/inorder-timing/config.ini  |  13 +-
 .../ref/mips/linux/inorder-timing/simout      |   8 +-
 .../ref/mips/linux/inorder-timing/stats.txt   |   8 +-
 .../ref/mips/linux/o3-timing/config.ini       |  11 +-
 .../00.hello/ref/mips/linux/o3-timing/simout  |   8 +-
 .../ref/mips/linux/o3-timing/stats.txt        |  28 +-
 .../ref/mips/linux/simple-atomic/config.ini   |  13 +-
 .../ref/mips/linux/simple-atomic/simout       |   8 +-
 .../ref/mips/linux/simple-atomic/stats.txt    |  26 +-
 .../mips/linux/simple-timing-ruby/config.ini  | 189 +++----
 .../ref/mips/linux/simple-timing-ruby/simout  |   8 +-
 .../mips/linux/simple-timing-ruby/stats.txt   |  24 +-
 .../ref/mips/linux/simple-timing/config.ini   |  11 +-
 .../ref/mips/linux/simple-timing/simout       |  12 +-
 .../ref/mips/linux/simple-timing/stats.txt    |  26 +-
 .../ref/power/linux/o3-timing/config.ini      |  11 +-
 .../00.hello/ref/power/linux/o3-timing/simerr |   2 +-
 .../00.hello/ref/power/linux/o3-timing/simout |   8 +-
 .../ref/power/linux/o3-timing/stats.txt       |  29 +-
 .../ref/power/linux/simple-atomic/config.ini  |  13 +-
 .../ref/power/linux/simple-atomic/simerr      |   2 +-
 .../ref/power/linux/simple-atomic/simout      |   8 +-
 .../ref/power/linux/simple-atomic/stats.txt   |  26 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |  13 +-
 .../ref/sparc/linux/simple-atomic/simout      |   8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |  26 +-
 .../sparc/linux/simple-timing-ruby/config.ini | 189 +++----
 .../sparc/linux/simple-timing-ruby/ruby.stats | 308 ++++++------
 .../ref/sparc/linux/simple-timing-ruby/simout |   8 +-
 .../sparc/linux/simple-timing-ruby/stats.txt  |  26 +-
 .../ref/sparc/linux/simple-timing/config.ini  |  11 +-
 .../ref/sparc/linux/simple-timing/simout      |  12 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  26 +-
 .../ref/x86/linux/o3-timing/config.ini        |   7 +
 .../00.hello/ref/x86/linux/o3-timing/simout   |   8 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  29 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   7 +
 .../ref/x86/linux/simple-atomic/simout        |   8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |  26 +-
 .../x86/linux/simple-timing-ruby/config.ini   |   8 +
 .../x86/linux/simple-timing-ruby/ruby.stats   |  47 +-
 .../ref/x86/linux/simple-timing-ruby/simout   |   8 +-
 .../x86/linux/simple-timing-ruby/stats.txt    |  26 +-
 .../ref/x86/linux/simple-timing/config.ini    |   7 +
 .../ref/x86/linux/simple-timing/simout        |   8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  26 +-
 .../ref/alpha/linux/o3-timing/config.ini      |  11 +-
 .../ref/alpha/linux/o3-timing/simout          |   8 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |  37 +-
 .../ref/sparc/linux/o3-timing/config.ini      |  11 +-
 .../ref/sparc/linux/o3-timing/simout          |   8 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |  28 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |  13 +-
 .../ref/sparc/linux/simple-atomic/simout      |   8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |  26 +-
 .../ref/sparc/linux/simple-timing/config.ini  |  11 +-
 .../ref/sparc/linux/simple-timing/simout      |  12 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  26 +-
 .../tsunami-simple-atomic-dual/config.ini     |  25 +-
 .../linux/tsunami-simple-atomic-dual/simerr   |   4 +
 .../linux/tsunami-simple-atomic-dual/simout   |  12 +-
 .../tsunami-simple-atomic-dual/stats.txt      |  44 +-
 .../linux/tsunami-simple-atomic/config.ini    |  25 +-
 .../alpha/linux/tsunami-simple-atomic/simerr  |   4 +
 .../alpha/linux/tsunami-simple-atomic/simout  |  12 +-
 .../linux/tsunami-simple-atomic/stats.txt     |  26 +-
 .../tsunami-simple-timing-dual/config.ini     |  25 +-
 .../linux/tsunami-simple-timing-dual/simerr   |   4 +
 .../linux/tsunami-simple-timing-dual/simout   |  12 +-
 .../tsunami-simple-timing-dual/stats.txt      |  44 +-
 .../linux/tsunami-simple-timing/config.ini    |  25 +-
 .../alpha/linux/tsunami-simple-timing/simerr  |   4 +
 .../alpha/linux/tsunami-simple-timing/simout  |  12 +-
 .../linux/tsunami-simple-timing/stats.txt     |  26 +-
 .../linux/realview-simple-atomic/config.ini   |  15 +-
 .../arm/linux/realview-simple-atomic/simout   |  12 +-
 .../linux/realview-simple-atomic/stats.txt    |  26 +-
 .../arm/linux/realview-simple-atomic/status   |   2 +-
 .../linux/realview-simple-timing/config.ini   |  11 +-
 .../arm/linux/realview-simple-timing/simout   |   8 +-
 .../linux/realview-simple-timing/stats.txt    |  26 +-
 .../realview-simple-timing/system.terminal    | Bin 3940 -> 3940 bytes
 .../ref/alpha/eio/simple-atomic/config.ini    |  11 +-
 .../ref/alpha/eio/simple-atomic/simout        |   8 +-
 .../ref/alpha/eio/simple-atomic/stats.txt     |  26 +-
 .../ref/alpha/eio/simple-timing/config.ini    |  11 +-
 .../ref/alpha/eio/simple-timing/simout        |   8 +-
 .../ref/alpha/eio/simple-timing/stats.txt     |  26 +-
 .../ref/alpha/eio/simple-atomic-mp/config.ini |  11 +-
 .../ref/alpha/eio/simple-atomic-mp/simout     |   8 +-
 .../ref/alpha/eio/simple-atomic-mp/stats.txt  |  80 ++-
 .../ref/alpha/eio/simple-timing-mp/config.ini |  11 +-
 .../ref/alpha/eio/simple-timing-mp/simerr     |   4 +-
 .../ref/alpha/eio/simple-timing-mp/simout     |   8 +-
 .../ref/alpha/eio/simple-timing-mp/stats.txt  |  80 ++-
 .../ref/sparc/linux/o3-timing-mp/config.ini   |  11 +-
 .../ref/sparc/linux/o3-timing-mp/simout       |   8 +-
 .../ref/sparc/linux/o3-timing-mp/stats.txt    |  92 +++-
 .../sparc/linux/simple-atomic-mp/config.ini   |  11 +-
 .../ref/sparc/linux/simple-atomic-mp/simout   |  12 +-
 .../sparc/linux/simple-atomic-mp/stats.txt    |  80 ++-
 .../sparc/linux/simple-timing-mp/config.ini   |  11 +-
 .../ref/sparc/linux/simple-timing-mp/simout   |  12 +-
 .../sparc/linux/simple-timing-mp/stats.txt    |  80 ++-
 .../ref/alpha/linux/memtest-ruby/config.ini   |  30 +-
 .../ref/alpha/linux/memtest-ruby/ruby.stats   | 461 +++++++++---------
 .../ref/alpha/linux/memtest-ruby/simerr       | 146 +++---
 .../ref/alpha/linux/memtest-ruby/simout       |  10 +-
 .../ref/alpha/linux/memtest-ruby/stats.txt    |  42 +-
 .../ref/alpha/linux/memtest/config.ini        |  11 +-
 .../50.memtest/ref/alpha/linux/memtest/simout |  10 +-
 .../ref/alpha/linux/memtest/stats.txt         |   6 +-
 .../ref/alpha/linux/rubytest-ruby/config.ini  |  81 +--
 .../ref/alpha/linux/rubytest-ruby/ruby.stats  |  42 +-
 .../ref/alpha/linux/rubytest-ruby/simout      |  10 +-
 .../ref/alpha/linux/rubytest-ruby/stats.txt   |   6 +-
 .../twosys-tsunami-simple-atomic/config.ini   |  50 +-
 .../linux/twosys-tsunami-simple-atomic/simerr |   4 +
 .../linux/twosys-tsunami-simple-atomic/simout |  14 +-
 .../twosys-tsunami-simple-atomic/stats.txt    |  86 +++-
 388 files changed, 6061 insertions(+), 2597 deletions(-)

diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index ed1344dd3..41c6a83e0 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index a359bdb55..5ab603e64 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:40:29
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:50
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 240486239..9ddf470e4 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 207877                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206352                       # Number of bytes of host memory used
-host_seconds                                  2720.61                       # Real time elapsed on the host
-host_tick_rate                               59832123                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 121046                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 226784                       # Number of bytes of host memory used
+host_seconds                                  4672.20                       # Real time elapsed on the host
+host_tick_rate                               34840083                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   565552443                       # Number of instructions simulated
 sim_seconds                                  0.162780                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    315794082                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 601856963                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                   1520                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls          1197610                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             563954763                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 114514042                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  153965363                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            325492829                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                       265                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       58                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           65560315                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 36252.118644                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      3177577                       #
 system.cpu.iew.memOrderViolationEvents          70243                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       943658                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        3659139                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                844691087                       # number of integer regfile reads
+system.cpu.int_regfile_writes               489153092                       # number of integer regfile writes
 system.cpu.ipc                               1.737170                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.737170                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    325492829                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.859166                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                    1679                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                3330                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses         1605                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes               1800                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              612363224                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         1543136462                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    595804344                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         671661588                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  619293624                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 605269413                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
@@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads          17165638                       # Nu
 system.cpu.memDep0.conflictingStores         12779208                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            126095826                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            42628898                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                        325559560                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         12578826                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      463854889                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents        31670463                       # Number of times rename has blocked due to IQ full
@@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles          115552585                       # Nu
 system.cpu.rename.RENAME:SquashCycles         9698747                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       37704265                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps          54254608                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups         1958                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    894826947                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          531                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           30                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts           73685603                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           29                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    958179178                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1334457472                       # The number of ROB writes
 system.cpu.timesIdled                            2072                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index d0f6032a2..355960d42 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
index 635701ab6..b96d561c3 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:31:02
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index 739ca9c21..4dfa82a45 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                6224890                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 232016                       # Number of bytes of host memory used
-host_seconds                                    96.69                       # Real time elapsed on the host
-host_tick_rate                             3112463113                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1697811                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 218112                       # Number of bytes of host memory used
+host_seconds                                   354.49                       # Real time elapsed on the host
+host_tick_rate                              848911876                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.300931                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        601861917                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  601861917                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     58554292                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
+system.cpu.num_fp_insts                          1520                       # number of float instructions
+system.cpu.num_fp_register_reads                  169                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  42                       # number of times the floating registers were written
+system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        601856964                       # Number of instructions executed
-system.cpu.num_refs                         153970296                       # Number of memory references
+system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
+system.cpu.num_int_insts                    563959696                       # number of integer instructions
+system.cpu.num_int_register_reads           801088993                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          463854847                       # number of times the integer registers were written
+system.cpu.num_load_insts                   114516673                       # Number of load instructions
+system.cpu.num_mem_refs                     153970296                       # number of memory refs
+system.cpu.num_store_insts                   39453623                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 6ed9b214f..5dbdc6426 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -157,7 +166,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
index 15443bcd3..5133de4f2 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:44:32
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:36
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index d095a4f5f..0f44a109b 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2723974                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 239668                       # Number of bytes of host memory used
-host_seconds                                   220.95                       # Real time elapsed on the host
-host_tick_rate                             3465167347                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 591495                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 225828                       # Number of bytes of host memory used
+host_seconds                                  1017.52                       # Real time elapsed on the host
+host_tick_rate                              752441266                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.765623                       # Number of seconds simulated
@@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   59341                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1531246064                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1531246064                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     58554292                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
+system.cpu.num_fp_insts                          1520                       # number of float instructions
+system.cpu.num_fp_register_reads                  169                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  42                       # number of times the floating registers were written
+system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        601856964                       # Number of instructions executed
-system.cpu.num_refs                         153970296                       # Number of memory references
+system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
+system.cpu.num_int_insts                    563959696                       # number of integer instructions
+system.cpu.num_int_register_reads           801088993                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          463854847                       # number of times the integer registers were written
+system.cpu.num_load_insts                   114516673                       # Number of load instructions
+system.cpu.num_mem_refs                     153970296                       # number of memory refs
+system.cpu.num_store_insts                   39453623                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
index 1ca0fc2d1..b2393d69d 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
index 913163576..c00731590 100755
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 02:01:01
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:59:50
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
index c8f41239c..3c92d3925 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 117336                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 251760                       # Number of bytes of host memory used
-host_seconds                                  5118.46                       # Real time elapsed on the host
-host_tick_rate                               42393313                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 115233                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 238284                       # Number of bytes of host memory used
+host_seconds                                  5211.87                       # Real time elapsed on the host
+host_tick_rate                               41633525                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   600581394                       # Number of instructions simulated
 sim_seconds                                  0.216988                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    415629341                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 600581394                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             531746837                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 148953025                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  219174038                       # Number of memory references committed
@@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            433097730                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses           75163464                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 35391.803279                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34026.104418                       # average ReadReq mshr miss latency
@@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     18357789                       #
 system.cpu.iew.memOrderViolationEvents         927620                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      1456086                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        3807013                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               1741733302                       # number of integer regfile reads
+system.cpu.int_regfile_writes               500762065                       # number of integer regfile writes
 system.cpu.ipc                               1.383903                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.383903                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    433097730                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.505667                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              661113885                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         1748261718                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    638555076                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         843800706                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  721925689                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 653424127                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                3886                       # Number of non-speculative instructions added to the IQ
@@ -470,7 +484,11 @@ system.cpu.memDep0.conflictingLoads          56143840                       # Nu
 system.cpu.memDep0.conflictingStores         33466008                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            184696678                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            88578802                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               960863166                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                   9367                       # number of misc regfile writes
 system.cpu.numCycles                        433976628                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         12394432                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      469246940                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents        63310884                       # Number of times rename has blocked due to IQ full
@@ -484,10 +502,14 @@ system.cpu.rename.RENAME:RunCycles          140765492                       # Nu
 system.cpu.rename.RENAME:SquashCycles        17468389                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       71980169                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps         110388314                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups           96                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   2146132242                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles        56297                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts         3959                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts          128598467                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts         3953                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   1130322956                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1461347493                       # The number of ROB writes
 system.cpu.timesIdled                           36486                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
index 04cb6159a..17d38a039 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -52,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
index dea298989..f425b3c91 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 19:16:15
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:00:03
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
index 6361eb760..fb68d0899 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2821771                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 253968                       # Number of bytes of host memory used
-host_seconds                                   212.84                       # Real time elapsed on the host
-host_tick_rate                             1410937507                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1026292                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 229344                       # Number of bytes of host memory used
+host_seconds                                   585.20                       # Real time elapsed on the host
+host_tick_rate                              513165203                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   600581394                       # Number of instructions simulated
 sim_seconds                                  0.300302                       # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        600604284                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  600604284                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        600581394                       # Number of instructions executed
-system.cpu.num_refs                         219174038                       # Number of memory references
+system.cpu.num_int_alu_accesses             531746837                       # Number of integer alu accesses
+system.cpu.num_int_insts                    531746837                       # number of integer instructions
+system.cpu.num_int_register_reads          1690709529                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          456307392                       # number of times the integer registers were written
+system.cpu.num_load_insts                   148953025                       # Number of load instructions
+system.cpu.num_mem_refs                     219174038                       # number of memory refs
+system.cpu.num_store_insts                   70221013                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
index 36e9f985b..de769cd56 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
index eabe42249..c1c8fcec5 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,7 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
 hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
index 38b916fc4..70559ac7d 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:44:50
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
index 8e10bdbf4..2b5fb88ae 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 652561                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 261720                       # Number of bytes of host memory used
-host_seconds                                   917.34                       # Real time elapsed on the host
-host_tick_rate                              868554806                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 452045                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 237056                       # Number of bytes of host memory used
+host_seconds                                  1324.25                       # Real time elapsed on the host
+host_tick_rate                              601669731                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   598619824                       # Number of instructions simulated
 sim_seconds                                  0.796760                       # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   57886                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1593519872                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1593519872                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        598619824                       # Number of instructions executed
-system.cpu.num_refs                         219174038                       # Number of memory references
+system.cpu.num_int_alu_accesses             531746837                       # Number of integer alu accesses
+system.cpu.num_int_insts                    531746837                       # number of integer instructions
+system.cpu.num_int_register_reads          1837343724                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          456308029                       # number of times the integer registers were written
+system.cpu.num_load_insts                   148953025                       # Number of load instructions
+system.cpu.num_mem_refs                     219174038                       # number of memory refs
+system.cpu.num_store_insts                   70221013                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 02ce84b2d..239140dc5 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index df93e233e..44a2a20b1 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 21:17:52
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 21:17:55
-M5 executing on zizzer
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:36
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index c2bc04472..2fc2b1f97 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 144426                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207996                       # Number of bytes of host memory used
-host_seconds                                  9732.45                       # Real time elapsed on the host
-host_tick_rate                               61799305                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 165526                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 228372                       # Number of bytes of host memory used
+host_seconds                                  8491.76                       # Real time elapsed on the host
+host_tick_rate                               70828550                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1405604152                       # Number of instructions simulated
 sim_seconds                                  0.601459                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total   1172142071                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                1489523295                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                8452036                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts            1319476388                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 402512844                       # Number of loads committed
 system.cpu.commit.COM:membars                   51356                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  569360986                       # Number of memory references committed
@@ -160,6 +163,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total           1202551977                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                  16952700                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 10422320                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses          173097327                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 35070.194986                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359                       # average ReadReq mshr miss latency
@@ -259,6 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     21427986                       #
 system.cpu.iew.memOrderViolationEvents         832421                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       648481                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        4876062                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               1994642284                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1296237136                       # number of integer regfile writes
 system.cpu.ipc                               1.168496                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.168496                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -350,6 +357,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total   1202551977                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.231945                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                 9139758                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads            17716192                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses      8503894                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes            9202883                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses             1476034706                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         4152007639                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses   1463994823                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        1798910142                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                 1603626285                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                1481928851                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded             3075919                       # Number of non-speculative instructions added to the IQ
@@ -430,7 +445,11 @@ system.cpu.memDep0.conflictingLoads         406523724                       # Nu
 system.cpu.memDep0.conflictingStores        165663867                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            468104279                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           188276128                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               596285867                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                2258933                       # number of misc regfile writes
 system.cpu.numCycles                       1202917849                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles        123850519                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1244770452                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:FullRegisterEvents     28358883                       # Number of times there has been no free registers
@@ -445,10 +464,14 @@ system.cpu.rename.RENAME:RunCycles          329588798                       # Nu
 system.cpu.rename.RENAME:SquashCycles        30410517                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles      217220436                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps         200424116                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups     33734828                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   2890766205                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles     57780774                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts      3037077                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts          385267398                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts      3036332                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   2859629611                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3448202738                       # The number of ROB writes
 system.cpu.timesIdled                           11390                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls
 
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index 25252561e..0b3b6266f 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip
+executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
index c99734c27..4748a164d 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:19:07
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:14:57
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index d04149323..16c920737 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1748575                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 185740                       # Number of bytes of host memory used
-host_seconds                                   851.85                       # Real time elapsed on the host
-host_tick_rate                              874289976                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1524596                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 219684                       # Number of bytes of host memory used
+host_seconds                                   977.00                       # Real time elapsed on the host
+host_tick_rate                              762300416                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
 sim_seconds                                  0.744764                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                744764119000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1489528239                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1489528239                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                8454127                       # Number of float alu accesses
+system.cpu.num_fp_insts                       8454127                       # number of float instructions
+system.cpu.num_fp_register_reads             16769332                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            10359244                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1489523295                       # Number of instructions executed
-system.cpu.num_refs                         569365767                       # Number of memory references
+system.cpu.num_int_alu_accesses            1319481298                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1319481298                       # number of integer instructions
+system.cpu.num_int_register_reads          2499743582                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1234411208                       # number of times the integer registers were written
+system.cpu.num_load_insts                   402515346                       # Number of load instructions
+system.cpu.num_mem_refs                     569365767                       # number of memory refs
+system.cpu.num_store_insts                  166850421                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 9772b8626..9789f7d05 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip
+executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index 78e3d8264..f2b4b3e16 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep 20 2010 15:04:49
-M5 revision 0c4a7d867247 7686 default qtip print-identical tip
-M5 started Sep 20 2010 16:28:00
-M5 executing on phenom
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:36
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 04e7c144d..8bc8178fc 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1333935                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197236                       # Number of bytes of host memory used
-host_seconds                                  1116.64                       # Real time elapsed on the host
-host_tick_rate                             1848636408                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 594721                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 227400                       # Number of bytes of host memory used
+host_seconds                                  2504.58                       # Real time elapsed on the host
+host_tick_rate                              824195004                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
 sim_seconds                                  2.064259                       # Number of seconds simulated
@@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   59035                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       4128517334                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 4128517334                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                8454127                       # Number of float alu accesses
+system.cpu.num_fp_insts                       8454127                       # number of float instructions
+system.cpu.num_fp_register_reads             16769332                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            10359244                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1489523295                       # Number of instructions executed
-system.cpu.num_refs                         569365767                       # Number of memory references
+system.cpu.num_int_alu_accesses            1319481298                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1319481298                       # number of integer instructions
+system.cpu.num_int_register_reads          2499743582                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1234411207                       # number of times the integer registers were written
+system.cpu.num_load_insts                   402515346                       # Number of load instructions
+system.cpu.num_mem_refs                     569365767                       # number of memory refs
+system.cpu.num_store_insts                  166850421                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
index f7f0c46d4..503c61f1c 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -481,7 +488,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
+cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
index f9fa6a62e..3dbb4b0b4 100755
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 16:34:44
-M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch
-M5 started Jan 31 2011 16:34:46
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:13
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 6441cfabc..05b37528b 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 136188                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231788                       # Number of bytes of host memory used
-host_seconds                                 11906.26                       # Real time elapsed on the host
-host_tick_rate                               64872637                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 168346                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 232444                       # Number of bytes of host memory used
+host_seconds                                  9631.89                       # Real time elapsed on the host
+host_tick_rate                               80190939                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1621493982                       # Number of instructions simulated
 sim_seconds                                  0.772390                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total   1511501895                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                1621493982                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                      0                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts            1621354492                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 419042125                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  607228182                       # Number of memory references committed
@@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total           1544565042                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                         2                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses          119630706                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 37171.926007                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121                       # average ReadReq mshr miss latency
@@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     22026294                       #
 system.cpu.iew.memOrderViolationEvents        3968261                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect         2078                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        6120468                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               4148897019                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1677631671                       # number of integer regfile writes
 system.cpu.ipc                               1.049659                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.049659                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass     24157467      1.43%      1.43% # Type of FU issued
@@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total   1544565042                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.096282                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                  8                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses             1669611057                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         4931850619                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses   1680860109                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        2080058032                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                 1849358797                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                1693515784                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  66                       # Number of non-speculative instructions added to the IQ
@@ -420,7 +434,10 @@ system.cpu.memDep0.conflictingLoads         289036318                       # Nu
 system.cpu.memDep0.conflictingStores        113016383                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            492554241                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           210212351                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               864820574                       # number of misc regfile reads
 system.cpu.numCycles                       1544781000                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         55578139                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1617994650                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents        65710608                       # Number of times rename has blocked due to IQ full
@@ -434,10 +451,14 @@ system.cpu.rename.RENAME:RunCycles          968560202                       # Nu
 system.cpu.rename.RENAME:SquashCycles        33063147                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles      126195704                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps         253681708                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups           32                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   5668050349                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles         2169                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           67                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts          186996608                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           71                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   3357159543                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3732197477                       # The number of ROB writes
 system.cpu.timesIdled                           45108                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 5a8f812f4..6c9d60230 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -54,7 +61,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index 2cf82dff0..1dd3bb0d2 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:38:48
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index c7162281a..ce8635d17 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1409865                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 219780                       # Number of bytes of host memory used
-host_seconds                                  1150.11                       # Real time elapsed on the host
-host_tick_rate                              838177430                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1066510                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223440                       # Number of bytes of host memory used
+host_seconds                                  1520.37                       # Real time elapsed on the host
+host_tick_rate                              634049597                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1621493983                       # Number of instructions simulated
 sim_seconds                                  0.963993                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                963992704000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1927985409                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1927985409                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     99478861                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1621493983                       # Number of instructions executed
-system.cpu.num_refs                         607228182                       # Number of memory references
+system.cpu.num_int_alu_accesses            1621354493                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1621354493                       # number of integer instructions
+system.cpu.num_int_register_reads          4883555465                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1617994650                       # number of times the integer registers were written
+system.cpu.num_load_insts                   419042125                       # Number of load instructions
+system.cpu.num_mem_refs                     607228182                       # number of memory refs
+system.cpu.num_store_insts                  188186057                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 56899b979..967d3d328 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -154,7 +161,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
+cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index c71548d66..889c6868b 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:35
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 8adfcec1a..46400c920 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1099985                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227480                       # Number of bytes of host memory used
-host_seconds                                  1474.11                       # Real time elapsed on the host
-host_tick_rate                             1223290364                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 685934                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 231240                       # Number of bytes of host memory used
+host_seconds                                  2363.92                       # Real time elapsed on the host
+host_tick_rate                              762824620                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1621493983                       # Number of instructions simulated
 sim_seconds                                  1.803259                       # Number of seconds simulated
@@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   58007                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       3606517174                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 3606517174                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     99478861                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1621493983                       # Number of instructions executed
-system.cpu.num_refs                         607228182                       # Number of memory references
+system.cpu.num_int_alu_accesses            1621354493                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1621354493                       # number of integer instructions
+system.cpu.num_int_register_reads          4883555465                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1617994650                       # number of times the integer registers were written
+system.cpu.num_load_insts                   419042125                       # Number of load instructions
+system.cpu.num_mem_refs                     607228182                       # number of memory refs
+system.cpu.num_store_insts                  188186057                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 70f885c82..b96a83286 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
@@ -19,6 +21,13 @@ readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.bridge]
 type=Bridge
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index 169564b5c..dcb4e3644 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 17:11:38
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 17:12:29
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:46:17
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:46:32
+M5 executing on burrito
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index cba8f3d91..3a665541f 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 123407                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 293584                       # Number of bytes of host memory used
-host_seconds                                   461.81                       # Real time elapsed on the host
-host_tick_rate                             4116011383                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  67358                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 313516                       # Number of bytes of host memory used
+host_seconds                                   846.09                       # Real time elapsed on the host
+host_tick_rate                             2246601111                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    56990797                       # Number of instructions simulated
 sim_seconds                                  1.900831                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu0.commit.COM:committed_per_cycle::min_value            0
 system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::total     78252168                       # Number of insts commited each cycle
 system.cpu0.commit.COM:count                 49773781                       # Number of instructions committed
+system.cpu0.commit.COM:fp_insts                245595                       # Number of committed floating point instructions.
+system.cpu0.commit.COM:function_calls          636046                       # Number of function calls committed.
+system.cpu0.commit.COM:int_insts             46098576                       # Number of committed integer instructions.
 system.cpu0.commit.COM:loads                  7894849                       # Number of loads committed
 system.cpu0.commit.COM:membars                 191655                       # Number of memory barriers committed
 system.cpu0.commit.COM:refs                  13318728                       # Number of memory references committed
@@ -248,6 +251,8 @@ system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::total            79523293                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fp_regfile_reads                   120916                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  122710                       # number of floating regfile writes
 system.cpu0.icache.ReadReq_accesses::0        7790772                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total      7790772                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100                       # average ReadReq miss latency
@@ -378,6 +383,8 @@ system.cpu0.iew.lsq.thread.0.squashedStores       419501                       #
 system.cpu0.iew.memOrderViolationEvents         38522                       # Number of memory order violations
 system.cpu0.iew.predictedNotTakenIncorrect       332064                       # Number of branches that were predicted not taken incorrectly
 system.cpu0.iew.predictedTakenIncorrect        379789                       # Number of branches that were predicted taken incorrectly
+system.cpu0.int_regfile_reads                66329266                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               36276231                       # number of integer regfile writes
 system.cpu0.ipc                              0.416037                       # IPC: Instructions Per Cycle
 system.cpu0.ipc_total                        0.416037                       # IPC: Total IPC of All Threads
 system.cpu0.iq.ISSUE:FU_type_0::No_OpClass         3762      0.01%      0.01% # Type of FU issued
@@ -469,6 +476,14 @@ system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::total     79523293                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:rate                    0.450743                       # Inst issue rate
+system.cpu0.iq.fp_alu_accesses                 260476                       # Number of floating point alu accesses
+system.cpu0.iq.fp_inst_queue_reads             508189                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       246844                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_writes            251997                       # Number of floating instruction queue writes
+system.cpu0.iq.int_alu_accesses              50944800                       # Number of integer alu accesses
+system.cpu0.iq.int_inst_queue_reads         181074941                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_wakeup_accesses     49741828                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.int_inst_queue_writes         60494151                       # Number of integer instruction queue writes
 system.cpu0.iq.iqInstsAdded                  52250537                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu0.iq.iqInstsIssued                 50826749                       # Number of instructions issued
 system.cpu0.iq.iqNonSpecInstsAdded            1722211                       # Number of non-speculative instructions added to the IQ
@@ -584,7 +599,11 @@ system.cpu0.memDep0.conflictingLoads          2324520                       # Nu
 system.cpu0.memDep0.conflictingStores         1920330                       # Number of conflicting stores.
 system.cpu0.memDep0.insertedLoads             9134564                       # Number of loads inserted to the mem dependence unit.
 system.cpu0.memDep0.insertedStores            5843380                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.misc_regfile_reads                1626369                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                787165                       # number of misc regfile writes
 system.cpu0.numCycles                       112762027                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.rename.RENAME:BlockCycles        12784616                       # Number of cycles rename is blocking
 system.cpu0.rename.RENAME:CommittedMaps      33979042                       # Number of HB maps that are committed
 system.cpu0.rename.RENAME:IQFullEvents        1006695                       # Number of times rename has blocked due to IQ full
@@ -598,10 +617,14 @@ system.cpu0.rename.RENAME:RunCycles          11035754                       # Nu
 system.cpu0.rename.RENAME:SquashCycles        1271125                       # Number of cycles rename is squashing
 system.cpu0.rename.RENAME:UnblockCycles       3987965                       # Number of cycles rename is unblocking
 system.cpu0.rename.RENAME:UndoneMaps          6000063                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:fp_rename_lookups       359001                       # Number of floating rename lookups
+system.cpu0.rename.RENAME:int_rename_lookups     72178524                       # Number of integer rename lookups
 system.cpu0.rename.RENAME:serializeStallCycles     16862175                       # count of cycles rename stalled for serializing inst
 system.cpu0.rename.RENAME:serializingInsts      1393641                       # count of serializing insts renamed
 system.cpu0.rename.RENAME:skidInsts          10087757                       # count of insts added to the skid buffer
 system.cpu0.rename.RENAME:tempSerializingInsts       207582                       # count of temporary serializing insts renamed
+system.cpu0.rob.rob_reads                   134196739                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  115376344                       # The number of ROB writes
 system.cpu0.timesIdled                        1187239                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu1.BPredUnit.BTBHits                 1159872                       # Number of BTB hits
@@ -632,6 +655,9 @@ system.cpu1.commit.COM:committed_per_cycle::min_value            0
 system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::total     17838555                       # Number of insts commited each cycle
 system.cpu1.commit.COM:count                 10605058                       # Number of instructions committed
+system.cpu1.commit.COM:fp_insts                116296                       # Number of committed floating point instructions.
+system.cpu1.commit.COM:function_calls          166623                       # Number of function calls committed.
+system.cpu1.commit.COM:int_insts              9814589                       # Number of committed integer instructions.
 system.cpu1.commit.COM:loads                  1991974                       # Number of loads committed
 system.cpu1.commit.COM:membars                  52733                       # Number of memory barriers committed
 system.cpu1.commit.COM:refs                   3376359                       # Number of memory references committed
@@ -841,6 +867,8 @@ system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::total            18144360                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fp_regfile_reads                    63103                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   63156                       # number of floating regfile writes
 system.cpu1.icache.ReadReq_accesses::0        1676515                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_accesses::total      1676515                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413                       # average ReadReq miss latency
@@ -971,6 +999,8 @@ system.cpu1.iew.lsq.thread.0.squashedStores       128329                       #
 system.cpu1.iew.memOrderViolationEvents         10653                       # Number of memory order violations
 system.cpu1.iew.predictedNotTakenIncorrect       104816                       # Number of branches that were predicted not taken incorrectly
 system.cpu1.iew.predictedTakenIncorrect         73994                       # Number of branches that were predicted taken incorrectly
+system.cpu1.int_regfile_reads                13933756                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                7611585                       # number of integer regfile writes
 system.cpu1.ipc                              0.513113                       # IPC: Instructions Per Cycle
 system.cpu1.ipc_total                        0.513113                       # IPC: Total IPC of All Threads
 system.cpu1.iq.ISSUE:FU_type_0::No_OpClass         3524      0.03%      0.03% # Type of FU issued
@@ -1062,6 +1092,14 @@ system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::total     18144360                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:rate                    0.557524                       # Inst issue rate
+system.cpu1.iq.fp_alu_accesses                 125165                       # Number of floating point alu accesses
+system.cpu1.iq.fp_inst_queue_reads             243017                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       117535                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_writes            119622                       # Number of floating instruction queue writes
+system.cpu1.iq.int_alu_accesses              10976050                       # Number of integer alu accesses
+system.cpu1.iq.int_inst_queue_reads          39966063                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_wakeup_accesses     10617468                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.int_inst_queue_writes         13352810                       # Number of integer instruction queue writes
 system.cpu1.iq.iqInstsAdded                  11252421                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu1.iq.iqInstsIssued                 10949829                       # Number of instructions issued
 system.cpu1.iq.iqNonSpecInstsAdded             555783                       # Number of non-speculative instructions added to the IQ
@@ -1166,7 +1204,11 @@ system.cpu1.memDep0.conflictingLoads           496033                       # Nu
 system.cpu1.memDep0.conflictingStores          413880                       # Number of conflicting stores.
 system.cpu1.memDep0.insertedLoads             2309588                       # Number of loads inserted to the mem dependence unit.
 system.cpu1.memDep0.insertedStores            1512714                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.misc_regfile_reads                 594436                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                255211                       # number of misc regfile writes
 system.cpu1.numCycles                        19640104                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.rename.RENAME:BlockCycles          522822                       # Number of cycles rename is blocking
 system.cpu1.rename.RENAME:CommittedMaps       7159583                       # Number of HB maps that are committed
 system.cpu1.rename.RENAME:IQFullEvents          32718                       # Number of times rename has blocked due to IQ full
@@ -1180,10 +1222,14 @@ system.cpu1.rename.RENAME:RunCycles           2359874                       # Nu
 system.cpu1.rename.RENAME:SquashCycles         305805                       # Number of cycles rename is squashing
 system.cpu1.rename.RENAME:UnblockCycles        801183                       # Number of cycles rename is unblocking
 system.cpu1.rename.RENAME:UndoneMaps          1329621                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:fp_rename_lookups       171444                       # Number of floating rename lookups
+system.cpu1.rename.RENAME:int_rename_lookups     15302029                       # Number of integer rename lookups
 system.cpu1.rename.RENAME:serializeStallCycles      5653749                       # count of cycles rename stalled for serializing inst
 system.cpu1.rename.RENAME:serializingInsts       515468                       # count of serializing insts renamed
 system.cpu1.rename.RENAME:skidInsts           2303190                       # count of insts added to the skid buffer
 system.cpu1.rename.RENAME:tempSerializingInsts        52722                       # count of temporary serializing insts renamed
+system.cpu1.rob.rob_reads                    29861070                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   24957765                       # The number of ROB writes
 system.cpu1.timesIdled                         194766                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 0ecea254a..838d9a364 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
@@ -19,6 +21,13 @@ readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.bridge]
 type=Bridge
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index cd15fbaad..bdb8a98f8 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 17:11:38
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 17:11:41
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:46:17
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:46:32
+M5 executing on burrito
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 549afdb19..e3a6bbb06 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 145689                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 291364                       # Number of bytes of host memory used
-host_seconds                                   364.14                       # Real time elapsed on the host
-host_tick_rate                             5126322811                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  66360                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 311288                       # Number of bytes of host memory used
+host_seconds                                   799.45                       # Real time elapsed on the host
+host_tick_rate                             2334981918                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    53051251                       # Number of instructions simulated
 sim_seconds                                  1.866703                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total     89231545                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                  56244349                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                 324384                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls           744090                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              52084301                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                   9107235                       # Number of loads committed
 system.cpu.commit.COM:membars                  227951                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                   15496318                       # Number of memory references committed
@@ -246,6 +249,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total             90747041                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                    164450                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   166718                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses::0         8856318                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total      8856318                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency::0 14954.328072                       # average ReadReq miss latency
@@ -376,6 +381,8 @@ system.cpu.iew.lsq.thread.0.squashedStores       554299                       #
 system.cpu.iew.memOrderViolationEvents          42661                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       406369                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect         431404                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                 74886349                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40928930                       # number of integer regfile writes
 system.cpu.ipc                               0.424064                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.424064                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass         7281      0.01%      0.01% # Type of FU issued
@@ -467,6 +474,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total     90747041                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.460931                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                  341243                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads              667907                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses       325691                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes             334133                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses               57747809                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          205867710                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses     56371536                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes          69251365                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                   59448706                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                  57663428                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded             2039751                       # Number of non-speculative instructions added to the IQ
@@ -578,7 +593,11 @@ system.cpu.memDep0.conflictingLoads           3018201                       # Nu
 system.cpu.memDep0.conflictingStores          2591237                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads             10628246                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores             6943382                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                 1993439                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 949389                       # number of misc regfile writes
 system.cpu.numCycles                        125102122                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         13297534                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       38227478                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         1065628                       # Number of times rename has blocked due to IQ full
@@ -592,10 +611,14 @@ system.cpu.rename.RENAME:RunCycles           12514369                       # Nu
 system.cpu.rename.RENAME:SquashCycles         1515496                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles        4654173                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps           7066231                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups       474968                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups     81738953                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles     19705456                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts      1694142                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts           11744700                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts       247271                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    152916375                       # The number of ROB reads
+system.cpu.rob.rob_writes                   131403689                       # The number of ROB writes
 system.cpu.timesIdled                         1310957                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
index 67f0de766..9285fee06 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,9 +493,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
index 43dc1d1fc..591032c8f 100755
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 03:03:04
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:58:27
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 674012633..390072636 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 109166                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 384348                       # Number of bytes of host memory used
-host_seconds                                   835.45                       # Real time elapsed on the host
-host_tick_rate                               67095197                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  65288                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 370872                       # Number of bytes of host memory used
+host_seconds                                  1396.92                       # Real time elapsed on the host
+host_tick_rate                               40127232                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91202735                       # Number of instructions simulated
 sim_seconds                                  0.056055                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    109380669                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                  91202735                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     48                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              72483223                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                  22585492                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                   27330336                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            112077802                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        75                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       47                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           12683523                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 36326.451613                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34504.457652                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores       788441                       #
 system.cpu.iew.memOrderViolationEvents           1330                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect        76117                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        1979748                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                246289928                       # number of integer regfile reads
+system.cpu.int_regfile_writes                76222702                       # number of integer regfile writes
 system.cpu.ipc                               0.813516                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.813516                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    112077802                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.888775                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      74                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                 144                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           66                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                 98                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              100131195                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          311849254                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses     96607706                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         112840034                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  102487226                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                  99639939                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded              553822                       # Number of non-speculative instructions added to the IQ
@@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads            436025                       # Nu
 system.cpu.memDep0.conflictingStores           249497                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads             24681131                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores             5533285                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               157552604                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1603309                       # number of misc regfile writes
 system.cpu.numCycles                        112109302                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles           294826                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       72061910                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents            4906                       # Number of times rename has blocked due to IQ full
@@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles           72730212                       # Nu
 system.cpu.rename.RENAME:SquashCycles         2697133                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles         723330                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps          11862848                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups          474                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    277458644                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles      5701177                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts       592742                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts            1065555                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts       576556                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    212048427                       # The number of ROB reads
+system.cpu.rob.rob_writes                   208775903                       # The number of ROB writes
 system.cpu.timesIdled                            1292                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
index bfff6943f..a584d29ed 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -52,14 +61,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
index d622d0388..34dd3ff53 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:40:32
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:24
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 9bb34897d..0d4b35c47 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2560594                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 386656                       # Number of bytes of host memory used
-host_seconds                                    35.62                       # Real time elapsed on the host
-host_tick_rate                             1522136495                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 937948                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 362060                       # Number of bytes of host memory used
+host_seconds                                    97.24                       # Real time elapsed on the host
+host_tick_rate                              557562760                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91202735                       # Number of instructions simulated
 sim_seconds                                  0.054216                       # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        108431099                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  108431099                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
+system.cpu.num_fp_insts                            48                       # number of float instructions
+system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         91202735                       # Number of instructions executed
-system.cpu.num_refs                          27330336                       # Number of memory references
+system.cpu.num_int_alu_accesses              72483223                       # Number of integer alu accesses
+system.cpu.num_int_insts                     72483223                       # number of integer instructions
+system.cpu.num_int_register_reads           234567931                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           72546720                       # number of times the integer registers were written
+system.cpu.num_load_insts                    22585492                       # Number of load instructions
+system.cpu.num_mem_refs                      27330336                       # number of memory refs
+system.cpu.num_store_insts                    4744844                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
index d78abde62..d7d6a4868 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,14 +161,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
index eabe42249..c1c8fcec5 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,7 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
 hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
index c45082899..b290f1d74 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:41:18
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
index bb2ffd900..5c965f81e 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 587679                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 394372                       # Number of bytes of host memory used
-host_seconds                                   155.15                       # Real time elapsed on the host
-host_tick_rate                              954493550                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 419592                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 369772                       # Number of bytes of host memory used
+host_seconds                                   217.30                       # Real time elapsed on the host
+host_tick_rate                              681491064                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91176087                       # Number of instructions simulated
 sim_seconds                                  0.148086                       # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                      32                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        296172438                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  296172438                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
+system.cpu.num_fp_insts                            48                       # number of float instructions
+system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         91176087                       # Number of instructions executed
-system.cpu.num_refs                          27330336                       # Number of memory references
+system.cpu.num_int_alu_accesses              72483223                       # Number of integer alu accesses
+system.cpu.num_int_insts                     72483223                       # number of integer instructions
+system.cpu.num_int_register_reads           257112085                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           72558730                       # number of times the integer registers were written
+system.cpu.num_load_insts                    22585492                       # Number of load instructions
+system.cpu.num_mem_refs                      27330336                       # number of memory refs
+system.cpu.num_store_insts                    4744844                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 06fed5d59..164664341 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,9 +66,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
index 6c4e0d9c5..a011c886e 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:27:41
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:14:01
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index 2eefb0962..282686242 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1458389                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 317928                       # Number of bytes of host memory used
-host_seconds                                   167.20                       # Real time elapsed on the host
-host_tick_rate                              730976871                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1159873                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 351876                       # Number of bytes of host memory used
+host_seconds                                   210.23                       # Real time elapsed on the host
+host_tick_rate                              581353978                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
 sim_seconds                                  0.122216                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                122215830000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        244431661                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  244431661                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
+system.cpu.num_fp_insts                         11630                       # number of float instructions
+system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        243835278                       # Number of instructions executed
-system.cpu.num_refs                         105711442                       # Number of memory references
+system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
+system.cpu.num_int_insts                    194726506                       # number of integer instructions
+system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          215451609                       # number of times the integer registers were written
+system.cpu.num_load_insts                    82803522                       # Number of load instructions
+system.cpu.num_mem_refs                     105711442                       # number of memory refs
+system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             443                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index e885b2b99..dd7acffe5 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,14 +161,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/mcf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
index b2d326b66..280cd1a31 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep 20 2010 15:04:49
-M5 revision 0c4a7d867247 7686 default qtip print-identical tip
-M5 started Sep 20 2010 16:31:43
-M5 executing on phenom
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:48
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index f56720371..1b0d7fe21 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1229097                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 329428                       # Number of bytes of host memory used
-host_seconds                                   198.39                       # Real time elapsed on the host
-host_tick_rate                             1826897848                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 483058                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 359588                       # Number of bytes of host memory used
+host_seconds                                   504.77                       # Real time elapsed on the host
+host_tick_rate                              718005180                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
 sim_seconds                                  0.362431                       # Number of seconds simulated
@@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                      40                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        724861774                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  724861774                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
+system.cpu.num_fp_insts                         11630                       # number of float instructions
+system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        243835278                       # Number of instructions executed
-system.cpu.num_refs                         105711442                       # Number of memory references
+system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
+system.cpu.num_int_insts                    194726506                       # number of integer instructions
+system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          215451608                       # number of times the integer registers were written
+system.cpu.num_load_insts                    82803522                       # Number of load instructions
+system.cpu.num_mem_refs                     105711442                       # number of memory refs
+system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             443                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
index 60f53a64a..8e006cde5 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -481,7 +488,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
+cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
index fde487a8e..bf0cc96de 100755
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 16:34:44
-M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch
-M5 started Jan 31 2011 16:34:46
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:24
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 8ba88fe5a..3db6ff161 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  76828                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 366252                       # Number of bytes of host memory used
-host_seconds                                  3621.00                       # Real time elapsed on the host
-host_tick_rate                               47136339                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  83481                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 366872                       # Number of bytes of host memory used
+host_seconds                                  3332.41                       # Real time elapsed on the host
+host_tick_rate                               51218385                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   278192519                       # Number of instructions simulated
 sim_seconds                                  0.170681                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    321793097                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 278192519                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     40                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             278186227                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                  90779388                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  122219139                       # Number of memory references committed
@@ -150,6 +153,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            341246945                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        44                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       31                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           39245397                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 37208.490566                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35316.192560                       # average ReadReq mshr miss latency
@@ -249,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      9599437                       #
 system.cpu.iew.memOrderViolationEvents        5520980                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect        16897                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        5373424                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                754340794                       # number of integer regfile reads
+system.cpu.int_regfile_writes               286169707                       # number of integer regfile writes
 system.cpu.ipc                               0.814950                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.814950                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass        16700      0.01%      0.01% # Type of FU issued
@@ -340,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    341246945                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.976510                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      55                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                 110                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           49                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                110                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              333424039                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         1008030271                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    317781500                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         504991584                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  389592403                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 333342642                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 455                       # Number of non-speculative instructions added to the IQ
@@ -419,7 +434,10 @@ system.cpu.memDep0.conflictingLoads          22358679                       # Nu
 system.cpu.memDep0.conflictingStores          3757180                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            131280417                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            41039188                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               204301939                       # number of misc regfile reads
 system.cpu.numCycles                        341361263                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles           486743                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      248344192                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents           12249                       # Number of times rename has blocked due to IQ full
@@ -432,10 +450,14 @@ system.cpu.rename.RENAME:RunCycles          222275258                       # Nu
 system.cpu.rename.RENAME:SquashCycles        19453848                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles         514692                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps         129004058                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups          291                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   1292599352                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles         5287                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts          454                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts             779091                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts          452                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    708961934                       # The number of ROB reads
+system.cpu.rob.rob_writes                   799263493                       # The number of ROB writes
 system.cpu.timesIdled                            5627                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             444                       # Number of system calls
 
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
index f7e610d03..f21f47f4d 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -54,7 +61,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
index dfdd5bece..e76d60819 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:12
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 82026f43b..bcab65c40 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 938582                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 354336                       # Number of bytes of host memory used
-host_seconds                                   296.40                       # Real time elapsed on the host
-host_tick_rate                              570013222                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 722489                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 358012                       # Number of bytes of host memory used
+host_seconds                                   385.05                       # Real time elapsed on the host
+host_tick_rate                              438776725                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   278192520                       # Number of instructions simulated
 sim_seconds                                  0.168950                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                168950072000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        337900145                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  337900145                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
+system.cpu.num_fp_insts                            40                       # number of float instructions
+system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        278192520                       # Number of instructions executed
-system.cpu.num_refs                         122219139                       # Number of memory references
+system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
+system.cpu.num_int_insts                    278186228                       # number of integer instructions
+system.cpu.num_int_register_reads           855210512                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          248344166                       # number of times the integer registers were written
+system.cpu.num_load_insts                    90779388                       # Number of load instructions
+system.cpu.num_mem_refs                     122219139                       # number of memory refs
+system.cpu.num_store_insts                   31439751                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             444                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
index 217d838ce..12f3ad44d 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -154,7 +161,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
index 68ecd8732..0b92276cc 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:12
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 7c84c26e1..cf6f03e98 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 734335                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 362052                       # Number of bytes of host memory used
-host_seconds                                   378.84                       # Real time elapsed on the host
-host_tick_rate                              976703915                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 424375                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 365728                       # Number of bytes of host memory used
+host_seconds                                   655.54                       # Real time elapsed on the host
+host_tick_rate                              564440982                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   278192520                       # Number of instructions simulated
 sim_seconds                                  0.370011                       # Number of seconds simulated
@@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   29460                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        740021680                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  740021680                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
+system.cpu.num_fp_insts                            40                       # number of float instructions
+system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        278192520                       # Number of instructions executed
-system.cpu.num_refs                         122219139                       # Number of memory references
+system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
+system.cpu.num_int_insts                    278186228                       # number of integer instructions
+system.cpu.num_int_register_reads           855210512                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          248344166                       # number of times the integer registers were written
+system.cpu.num_load_insts                    90779388                       # Number of load instructions
+system.cpu.num_mem_refs                     122219139                       # number of memory refs
+system.cpu.num_store_insts                   31439751                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             444                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
index 5f7dcc6cf..92faf41fb 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,9 +493,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
index 7fcfd6a75..b1ee33712 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 03:20:30
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
index b9adedb70..5862f2750 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  95936                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 255716                       # Number of bytes of host memory used
-host_seconds                                  5851.87                       # Real time elapsed on the host
-host_tick_rate                               62464794                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  89247                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 242220                       # Number of bytes of host memory used
+host_seconds                                  6290.45                       # Real time elapsed on the host
+host_tick_rate                               58109668                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   561403855                       # Number of instructions simulated
 sim_seconds                                  0.365536                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    660408748                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 561403855                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             464140463                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 128127024                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  184987501                       # Number of memory references committed
@@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            726668486                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses          122785155                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 13335.070892                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  9658.160050                       # average ReadReq mshr miss latency
@@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     83223254                       #
 system.cpu.iew.memOrderViolationEvents         352056                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect     15636111                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       14467473                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               1624866525                       # number of integer regfile reads
+system.cpu.int_regfile_writes               504061562                       # number of integer regfile writes
 system.cpu.ipc                               0.767919                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.767919                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    726668486                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.039903                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                     140                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                 276                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                652                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              771704903                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         2266614625                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    674936607                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        1350317509                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  960829595                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 760243815                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded              162257                       # Number of non-speculative instructions added to the IQ
@@ -465,7 +479,11 @@ system.cpu.memDep0.conflictingLoads          60170710                       # Nu
 system.cpu.memDep0.conflictingStores         74734099                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            200154824                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           140083731                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads              1169165868                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 344748                       # number of misc regfile writes
 system.cpu.numCycles                        731071595                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles          7125233                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      435368498                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         5221350                       # Number of times rename has blocked due to IQ full
@@ -479,10 +497,14 @@ system.cpu.rename.RENAME:RunCycles          326862324                       # Nu
 system.cpu.rename.RENAME:SquashCycles        66259738                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       15428382                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps         278321764                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups         2110                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   2644674034                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles      1706138                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts       233255                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts           48704887                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts       185624                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   1617861624                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1988299741                       # The number of ROB writes
 system.cpu.timesIdled                           93433                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
index 8f051c01c..8b55eca4f 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -52,14 +61,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
index e187e6939..c27562976 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:37:50
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 3d8390b34..0871fb1fa 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2845430                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 257528                       # Number of bytes of host memory used
-host_seconds                                   197.30                       # Real time elapsed on the host
-host_tick_rate                             1448130657                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1052675                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 232888                       # Number of bytes of host memory used
+host_seconds                                   533.31                       # Real time elapsed on the host
+host_tick_rate                              535740490                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   561403855                       # Number of instructions simulated
 sim_seconds                                  0.285717                       # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        571433624                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  571433624                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        561403855                       # Number of instructions executed
-system.cpu.num_refs                         184987503                       # Number of memory references
+system.cpu.num_int_alu_accesses             464140465                       # Number of integer alu accesses
+system.cpu.num_int_insts                    464140465                       # number of integer instructions
+system.cpu.num_int_register_reads          1370673061                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          415936275                       # number of times the integer registers were written
+system.cpu.num_load_insts                   128127024                       # Number of load instructions
+system.cpu.num_mem_refs                     184987503                       # number of memory refs
+system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
index 2acf6aa8b..9596a7281 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,14 +161,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
index eabe42249..cdafa164c 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
 hack: be nice to actually delete the event here
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
index 76b9031da..db8a10df5 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 19:30:07
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:00:20
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
index d49ea7a07..5187afa41 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 698342                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 265248                       # Number of bytes of host memory used
-host_seconds                                   801.14                       # Real time elapsed on the host
-host_tick_rate                              898558125                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 427899                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 240600                       # Number of bytes of host memory used
+host_seconds                                  1307.48                       # Real time elapsed on the host
+host_tick_rate                              550579326                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   559470527                       # Number of instructions simulated
 sim_seconds                                  0.719872                       # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle          510281834000                       # Cy
 system.cpu.l2cache.writebacks                  172310                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1439744848                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1439744848                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        559470527                       # Number of instructions executed
-system.cpu.num_refs                         184987503                       # Number of memory references
+system.cpu.num_int_alu_accesses             464140465                       # Number of integer alu accesses
+system.cpu.num_int_insts                    464140465                       # number of integer instructions
+system.cpu.num_int_register_reads          1497198689                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          415939738                       # number of times the integer registers were written
+system.cpu.num_load_insts                   128127024                       # Number of load instructions
+system.cpu.num_mem_refs                     184987503                       # number of memory refs
+system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
index aa5254a3b..8363ae747 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -481,7 +488,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
+cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
index 6e2ddc167..4d3b5f29b 100755
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 16:34:44
-M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch
-M5 started Jan 31 2011 16:34:46
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:13
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
index c8db50488..c39e8dfae 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 123365                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 239740                       # Number of bytes of host memory used
-host_seconds                                 12393.99                       # Real time elapsed on the host
-host_tick_rate                               65919204                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 160923                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 240360                       # Number of bytes of host memory used
+host_seconds                                  9501.35                       # Real time elapsed on the host
+host_tick_rate                               85987979                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1528988756                       # Number of instructions simulated
 sim_seconds                                  0.817002                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total   1552269342                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                1528988756                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                      0                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts            1528317614                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 384102160                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  533262345                       # Number of memory references committed
@@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total           1623905370                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        10                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses          165973622                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 22741.617211                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 19372.661290                       # average ReadReq mshr miss latency
@@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     44929168                       #
 system.cpu.iew.memOrderViolationEvents       11954619                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       280770                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       18292736                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               3876226209                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1582892637                       # number of integer regfile writes
 system.cpu.ipc                               0.935731                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.935731                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass      1927969      0.11%      0.11% # Type of FU issued
@@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total   1623905370                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.060682                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      24                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  48                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                 68                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses             1732259326                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         5091250901                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses   1694146357                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        2453039449                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                 1988096819                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                1733158148                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 579                       # Number of non-speculative instructions added to the IQ
@@ -430,7 +444,10 @@ system.cpu.memDep0.conflictingLoads         151128770                       # Nu
 system.cpu.memDep0.conflictingStores         47539398                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            508224738                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           194089353                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               947795380                       # number of misc regfile reads
 system.cpu.numCycles                       1634004079                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         11181498                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1427299027                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         8162354                       # Number of times rename has blocked due to IQ full
@@ -444,10 +461,14 @@ system.cpu.rename.RENAME:RunCycles         1095363349                       # Nu
 system.cpu.rename.RENAME:SquashCycles        71636028                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       14962968                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps         538631225                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups          168                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   6064799758                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles         6110                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts          566                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts           21122292                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts          563                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   3532180532                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4048956705                       # The number of ROB writes
 system.cpu.timesIdled                          351337                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             551                       # Number of system calls
 
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
index 2edd32f29..fdc891c59 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -54,7 +61,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index 1a82abfd9..70ab31a10 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:12
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 016faf2ec..836ed1519 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1495739                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 223620                       # Number of bytes of host memory used
-host_seconds                                  1022.23                       # Real time elapsed on the host
-host_tick_rate                              865978759                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 904614                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 227300                       # Number of bytes of host memory used
+host_seconds                                  1690.21                       # Real time elapsed on the host
+host_tick_rate                              523739013                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1528988757                       # Number of instructions simulated
 sim_seconds                                  0.885229                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                885229360000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1770458721                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1770458721                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     92658800                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1528988757                       # Number of instructions executed
-system.cpu.num_refs                         533262345                       # Number of memory references
+system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1528317615                       # number of integer instructions
+system.cpu.num_int_register_reads          4418676175                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1427299027                       # number of times the integer registers were written
+system.cpu.num_load_insts                   384102160                       # Number of load instructions
+system.cpu.num_mem_refs                     533262345                       # number of memory refs
+system.cpu.num_store_insts                  149160185                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             551                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index fc75460ef..4c1fe374d 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -154,7 +161,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index 2f7e6c58c..9e491e500 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:36:47
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index 630224d3a..2cd323573 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1108188                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231336                       # Number of bytes of host memory used
-host_seconds                                  1379.72                       # Real time elapsed on the host
-host_tick_rate                             1202222105                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 738382                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 235020                       # Number of bytes of host memory used
+host_seconds                                  2070.73                       # Real time elapsed on the host
+host_tick_rate                              801036637                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1528988757                       # Number of instructions simulated
 sim_seconds                                  1.658730                       # Number of seconds simulated
@@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle          896565143000                       # Cy
 system.cpu.l2cache.writebacks                  411709                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       3317459208                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 3317459208                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     92658800                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1528988757                       # Number of instructions executed
-system.cpu.num_refs                         533262345                       # Number of memory references
+system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1528317615                       # number of integer instructions
+system.cpu.num_int_register_reads          4418676175                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1427299027                       # number of times the integer registers were written
+system.cpu.num_load_insts                   384102160                       # Number of load instructions
+system.cpu.num_mem_refs                     533262345                       # number of memory refs
+system.cpu.num_store_insts                  149160185                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             551                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 73c8936cc..e6dd679c1 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
index 1688d3208..9a3fdb284 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:25:09
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:47
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index eb0b216c3..05fbc791d 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 178067                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 212832                       # Number of bytes of host memory used
-host_seconds                                  2109.17                       # Real time elapsed on the host
-host_tick_rate                               64635199                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  86954                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 233264                       # Number of bytes of host memory used
+host_seconds                                  4319.23                       # Real time elapsed on the host
+host_tick_rate                               31562755                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   375574819                       # Number of instructions simulated
 sim_seconds                                  0.136327                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    256761438                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 398664594                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts              155295106                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls          8007752                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             316365851                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                  94754489                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  168275218                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            272512875                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                 161565122                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                106206809                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           64427463                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 32238.031366                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 30836.486832                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     19394112                       #
 system.cpu.iew.memOrderViolationEvents         663165                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      1101512                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        5016228                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                421360455                       # number of integer regfile reads
+system.cpu.int_regfile_writes               182139619                       # number of integer regfile writes
 system.cpu.ipc                               1.377479                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.377479                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass        33581      0.01%      0.01% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    272512875                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.578500                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses               175992487                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads           346671239                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses    165916628                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes          231922736                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              262987844                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          796105773                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    251613948                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         330463092                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  469247183                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 430384006                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 241                       # Number of non-speculative instructions added to the IQ
@@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads          71937561                       # Nu
 system.cpu.memDep0.conflictingStores         54246192                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            117580442                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            92914841                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                        272653822                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         10643219                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      259532341                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         2331141                       # Number of times rename has blocked due to IQ full
@@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles           96677987                       # Nu
 system.cpu.rename.RENAME:SquashCycles        15751437                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       10596756                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps          78407825                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups    326649614                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    361910200                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles       367264                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts        37559                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts           23060243                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts          258                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    740781417                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1009223784                       # The number of ROB writes
 system.cpu.timesIdled                            3093                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls
 
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index a541de94f..5f40a4aa8 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
index f259e0f2b..ea7dd73a3 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 getting pixel output filename pixels_out.cook
 opening control file chair.control.cook
 opening camera file chair.camera
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
index 602c1e755..96b5bf3c9 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:31:02
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:38
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index aa6437370..6fcc67a34 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4732897                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 238480                       # Number of bytes of host memory used
-host_seconds                                    84.23                       # Real time elapsed on the host
-host_tick_rate                             2366444186                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1382202                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 224632                       # Number of bytes of host memory used
+host_seconds                                   288.43                       # Real time elapsed on the host
+host_tick_rate                              691100750                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_seconds                                  0.199332                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        398664824                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  398664824                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     25997787                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
+system.cpu.num_fp_insts                     155295119                       # number of float instructions
+system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
+system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        398664595                       # Number of instructions executed
-system.cpu.num_refs                         168275274                       # Number of memory references
+system.cpu.num_int_alu_accesses             316365907                       # Number of integer alu accesses
+system.cpu.num_int_insts                    316365907                       # number of integer instructions
+system.cpu.num_int_register_reads           372938760                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          159335860                       # number of times the integer registers were written
+system.cpu.num_load_insts                    94754510                       # Number of load instructions
+system.cpu.num_mem_refs                     168275274                       # number of memory refs
+system.cpu.num_store_insts                   73520764                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index dee4088d8..91f994c0c 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -157,7 +166,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
index f259e0f2b..ea7dd73a3 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 getting pixel output filename pixels_out.cook
 opening control file chair.control.cook
 opening camera file chair.camera
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
index 3f5e4009e..4f3149cad 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:41:16
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:38
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 70d7495a6..31ad19d58 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2252516                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 246196                       # Number of bytes of host memory used
-host_seconds                                   176.99                       # Real time elapsed on the host
-host_tick_rate                             3205571054                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 531142                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 232344                       # Number of bytes of host memory used
+host_seconds                                   750.58                       # Real time elapsed on the host
+host_tick_rate                              755872580                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_seconds                                  0.567343                       # Number of seconds simulated
@@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1134686340                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1134686340                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     25997790                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
+system.cpu.num_fp_insts                     155295119                       # number of float instructions
+system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
+system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        398664609                       # Number of instructions executed
-system.cpu.num_refs                         168275276                       # Number of memory references
+system.cpu.num_int_alu_accesses             316365921                       # Number of integer alu accesses
+system.cpu.num_int_insts                    316365921                       # number of integer instructions
+system.cpu.num_int_register_reads           372938779                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          159335870                       # number of times the integer registers were written
+system.cpu.num_load_insts                    94754511                       # Number of load instructions
+system.cpu.num_mem_refs                     168275276                       # number of memory refs
+system.cpu.num_store_insts                   73520765                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
index 05c074be9..5e5332f9b 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
index 026fec0e6..da6bef881 100755
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 03:29:33
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:35
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
index 432c33c36..6d2d3d9a2 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 100561                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 266348                       # Number of bytes of host memory used
-host_seconds                                  3428.53                       # Real time elapsed on the host
-host_tick_rate                               62832373                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  72451                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 252856                       # Number of bytes of host memory used
+host_seconds                                  4758.76                       # Real time elapsed on the host
+host_tick_rate                               45268689                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   344777955                       # Number of instructions simulated
 sim_seconds                                  0.215423                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    417225954                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 344777955                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts              114216705                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             283262899                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                  94652977                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  177028572                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            430736614                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                 185889152                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                130863264                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           45676058                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 11498.094859                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  7998.634691                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     11245258                       #
 system.cpu.iew.memOrderViolationEvents           6487                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      2859204                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        7562654                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                857434842                       # number of integer regfile reads
+system.cpu.int_regfile_writes               187420899                       # number of integer regfile writes
 system.cpu.ipc                               0.800235                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.800235                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    430736614                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.876078                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses               122762429                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads           242026964                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses    116081453                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes          130324765                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              261691284                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          951420966                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    249709151                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         308466887                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  389801085                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 377454477                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded             3540937                       # Number of non-speculative instructions added to the IQ
@@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads          34606299                       # Nu
 system.cpu.memDep0.conflictingStores         43565672                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            108215524                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            93620853                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads              1021297951                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               43097547                       # number of misc regfile writes
 system.cpu.numCycles                        430845860                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles          2009946                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      340171955                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents            2410                       # Number of times rename has blocked due to IQ full
@@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles          159405057                       # Nu
 system.cpu.rename.RENAME:SquashCycles        13510660                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       15892138                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps          73676716                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups    836456573                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    842367236                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles    117198109                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts     12788197                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts           37692287                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts      3543781                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    805385527                       # The number of ROB reads
+system.cpu.rob.rob_writes                   800205983                       # The number of ROB writes
 system.cpu.timesIdled                            2211                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
 
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
index ac380ff0f..a5b41f00b 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -52,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
index f5391da34..934921226 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 19:19:59
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 4b61fce38..f26b1f1eb 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2280191                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 262416                       # Number of bytes of host memory used
-host_seconds                                   151.21                       # Real time elapsed on the host
-host_tick_rate                             1390158822                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 829275                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 237784                       # Number of bytes of host memory used
+host_seconds                                   415.76                       # Real time elapsed on the host
+host_tick_rate                              505582613                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   344777955                       # Number of instructions simulated
 sim_seconds                                  0.210200                       # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        420400644                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  420400644                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
+system.cpu.num_fp_insts                     114216705                       # number of float instructions
+system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        344777955                       # Number of instructions executed
-system.cpu.num_refs                         177028576                       # Number of memory references
+system.cpu.num_int_alu_accesses             283262903                       # Number of integer alu accesses
+system.cpu.num_int_insts                    283262903                       # number of integer instructions
+system.cpu.num_int_register_reads          1207980255                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          211974282                       # number of times the integer registers were written
+system.cpu.num_load_insts                    94652977                       # Number of load instructions
+system.cpu.num_mem_refs                     177028576                       # number of memory refs
+system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
index 3b627362e..9c15d1771 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
index 0de362399..fc990d9e5 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
@@ -1,12 +1,20 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
 getting pixel output filename pixels_out.cook
 opening control file chair.control.cook
 opening camera file chair.camera
 opening surfaces file chair.surfaces
 reading data
 processing 8parts
-Grid measure is 6 by 3.0001 by 6
+Grid measure is warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+6 by 3.0001 by 6
 cell dimension is 0.863065
 Creating grid for list of length 21
 Grid size = 7 by 4 by 7
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
index 26d019ac6..1f52687a3 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 19:23:59
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:00:13
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
index 9ac8b63de..b6636f892 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 520438                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 270128                       # Number of bytes of host memory used
-host_seconds                                   661.75                       # Real time elapsed on the host
-host_tick_rate                              794599336                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 394687                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 245492                       # Number of bytes of host memory used
+host_seconds                                   872.59                       # Real time elapsed on the host
+host_tick_rate                              602604420                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   344399678                       # Number of instructions simulated
 sim_seconds                                  0.525826                       # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1051651768                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1051651768                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
+system.cpu.num_fp_insts                     114216705                       # number of float instructions
+system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        344399678                       # Number of instructions executed
-system.cpu.num_refs                         177028576                       # Number of memory references
+system.cpu.num_int_alu_accesses             283262902                       # Number of integer alu accesses
+system.cpu.num_int_insts                    283262902                       # number of integer instructions
+system.cpu.num_int_register_reads          1344047799                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          212263713                       # number of times the integer registers were written
+system.cpu.num_load_insts                    94652977                       # Number of load instructions
+system.cpu.num_mem_refs                     177028576                       # number of memory refs
+system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index cbf5155cb..be2448eae 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 7d9e000fc..79d6b4e40 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:24:57
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:38
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 63c7a2e36..375e28f85 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 156459                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213156                       # Number of bytes of host memory used
-host_seconds                                 11651.86                       # Real time elapsed on the host
-host_tick_rate                               60063670                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 179836                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 233568                       # Number of bytes of host memory used
+host_seconds                                 10137.27                       # Real time elapsed on the host
+host_tick_rate                               69037678                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_seconds                                  0.699854                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total   1301001982                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                2008987604                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts               71824891                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls         39955347                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts            1778941351                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 511070026                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  721864922                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total           1399572740                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                  79145201                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 52656290                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses          346350693                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 15859.786377                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.165644                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     92047647                       #
 system.cpu.iew.memOrderViolationEvents           3569                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       787992                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       30086110                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               2538504149                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1455287800                       # number of integer regfile writes
 system.cpu.ipc                               1.302446                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.302446                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass         2752      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total   1399572740                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.488357                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                76224315                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads           150190709                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses     73940522                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes           77634670                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses             2044010329                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         5465284170                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses   1924287563                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        2854317928                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                 2377509698                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                2083264453                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  67                       # Number of non-speculative instructions added to the IQ
@@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads         118268475                       # Nu
 system.cpu.memDep0.conflictingStores         21018090                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            651766159                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           302842543                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                       1399707092                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         19659094                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1384969070                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents          672257                       # Number of times rename has blocked due to IQ full
@@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles          542782008                       # Nu
 system.cpu.rename.RENAME:SquashCycles        98570758                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       13186877                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps         495793350                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups    113413742                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   3181273204                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles        21539                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts         2826                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts           26818332                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           73                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   3921848396                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5489856325                       # The number of ROB writes
 system.cpu.timesIdled                            3665                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
 
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index 233f88432..f80631f28 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
index 1fdd222af..abaf1cb79 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(0, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 7fa3cc9e1..b7ecd550d 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:59:54
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index c5afc67b3..855c5964e 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5515431                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 238276                       # Number of bytes of host memory used
-host_seconds                                   364.25                       # Real time elapsed on the host
-host_tick_rate                             2758309260                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1477901                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 224424                       # Number of bytes of host memory used
+host_seconds                                  1359.35                       # Real time elapsed on the host
+host_tick_rate                              739109964                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  1.004711                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       2009421175                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 2009421175                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    172959296                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
+system.cpu.num_fp_insts                      71831671                       # number of float instructions
+system.cpu.num_fp_register_reads             77066699                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            52280770                       # number of times the floating registers were written
+system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       2008987605                       # Number of instructions executed
-system.cpu.num_refs                         722298387                       # Number of memory references
+system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1779374816                       # number of integer instructions
+system.cpu.num_int_register_reads          2314712013                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1332688300                       # number of times the integer registers were written
+system.cpu.num_load_insts                   511488910                       # Number of load instructions
+system.cpu.num_mem_refs                     722298387                       # number of memory refs
+system.cpu.num_store_insts                  210809477                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index f0aef1670..9be1cb679 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -157,7 +166,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
index 1fdd222af..abaf1cb79 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(0, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index fcac3af61..03731b56d 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 22:06:01
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:38
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 0d35bbf18..c88cbd8f6 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2134538                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 246068                       # Number of bytes of host memory used
-host_seconds                                   941.18                       # Real time elapsed on the host
-host_tick_rate                             2989292617                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 584935                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 232204                       # Number of bytes of host memory used
+host_seconds                                  3434.55                       # Real time elapsed on the host
+host_tick_rate                              819166202                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  2.813468                       # Number of seconds simulated
@@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   66898                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       5626935684                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 5626935684                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    172959296                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
+system.cpu.num_fp_insts                      71831671                       # number of float instructions
+system.cpu.num_fp_register_reads             77066699                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            52280770                       # number of times the floating registers were written
+system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       2008987605                       # Number of instructions executed
-system.cpu.num_refs                         722298387                       # Number of memory references
+system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1779374816                       # number of integer instructions
+system.cpu.num_int_register_reads          2314712013                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1332688300                       # number of times the integer registers were written
+system.cpu.num_load_insts                   511488910                       # Number of load instructions
+system.cpu.num_mem_refs                     722298387                       # number of memory refs
+system.cpu.num_store_insts                  210809477                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 0ccefb2ad..3820d828c 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
index 32de132ae..ddea5239d 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 03:34:31
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:00:50
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 46557403f..a1dda945d 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 126560                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 258084                       # Number of bytes of host memory used
-host_seconds                                 14568.38                       # Real time elapsed on the host
-host_tick_rate                               75985562                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 139604                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 244852                       # Number of bytes of host memory used
+host_seconds                                 13207.13                       # Real time elapsed on the host
+host_tick_rate                               83817309                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1843766922                       # Number of instructions simulated
 sim_seconds                                  1.106986                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total   2026425019                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                1843766922                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts               52289415                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts            1619025870                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 631405848                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  908401145                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total           2213708436                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                  66048246                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 52282096                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses          400588369                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency  8967.410787                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  5871.276669                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores    210074657                       #
 system.cpu.iew.memOrderViolationEvents        2755264                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect     45730558                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       48147488                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               5403725947                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1668305359                       # number of integer regfile writes
 system.cpu.ipc                               0.832787                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.832787                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total   2213708436                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.104443                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                64689412                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads           126628637                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses     56420382                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes          101846831                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses             2441240602                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         7046560079                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses   2188392805                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        4055397012                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                 3002770977                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                2445205760                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded             9835077                       # Number of non-speculative instructions added to the IQ
@@ -470,7 +485,11 @@ system.cpu.memDep0.conflictingLoads          48375882                       # Nu
 system.cpu.memDep0.conflictingStores        167873780                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            976823890                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           487069954                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads              4207984120                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               14227476                       # number of misc regfile writes
 system.cpu.numCycles                       2213972582                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         17658494                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1482327508                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         4825678                       # Number of times rename has blocked due to IQ full
@@ -484,10 +503,14 @@ system.cpu.rename.RENAME:RunCycles          880460602                       # Nu
 system.cpu.rename.RENAME:SquashCycles       187283417                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       23975327                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps        1203658997                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups    485863672                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   8770011391                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles    185210215                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts     19466962                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts          226114375                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts     13965391                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   4997592572                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6212467818                       # The number of ROB writes
 system.cpu.timesIdled                           87015                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
 
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index ecd3fff8c..97cb6c6e4 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -52,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
index 6f1aaca4d..e6fdba858 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 19:04:52
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:24
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 62cb1fa61..807917422 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2747008                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 259372                       # Number of bytes of host memory used
-host_seconds                                   671.19                       # Real time elapsed on the host
-host_tick_rate                             1377891283                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 966272                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 234680                       # Number of bytes of host memory used
+host_seconds                                  1908.12                       # Real time elapsed on the host
+host_tick_rate                              484679459                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1843766922                       # Number of instructions simulated
 sim_seconds                                  0.924828                       # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1849656818                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1849656818                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
+system.cpu.num_fp_insts                      52289415                       # number of float instructions
+system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1843766922                       # Number of instructions executed
-system.cpu.num_refs                         908401146                       # Number of memory references
+system.cpu.num_int_alu_accesses            1619025871                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1619025871                       # number of integer instructions
+system.cpu.num_int_register_reads          4830749754                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1365217022                       # number of times the integer registers were written
+system.cpu.num_load_insts                   631405848                       # Number of load instructions
+system.cpu.num_mem_refs                     908401146                       # number of memory refs
+system.cpu.num_store_insts                  276995298                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 32ec6dcf7..dfd8de545 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
index 805a6606f..d834843e9 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
 warn: fcntl64(3, 2) passed through to host
 For more information see: http://www.m5sim.org/warn/a55e2c46
 hack: be nice to actually delete the event here
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
index 850a4596a..b556adbf3 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:41:18
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 2158e673a..1e3225702 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 628678                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 267092                       # Number of bytes of host memory used
-host_seconds                                  2915.13                       # Real time elapsed on the host
-host_tick_rate                              812964589                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 494422                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 242392                       # Number of bytes of host memory used
+host_seconds                                  3706.70                       # Real time elapsed on the host
+host_tick_rate                              639353926                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1832675505                       # Number of instructions simulated
 sim_seconds                                  2.369896                       # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   66099                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       4739792356                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 4739792356                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
+system.cpu.num_fp_insts                      52289415                       # number of float instructions
+system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1832675505                       # Number of instructions executed
-system.cpu.num_refs                         908401146                       # Number of memory references
+system.cpu.num_int_alu_accesses            1619025871                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1619025871                       # number of integer instructions
+system.cpu.num_int_register_reads          5455211671                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1365288731                       # number of times the integer registers were written
+system.cpu.num_load_insts                   631405848                       # Number of load instructions
+system.cpu.num_mem_refs                     908401146                       # number of memory refs
+system.cpu.num_store_insts                  276995298                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index 83b3078ca..46d47f481 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=InOrderCPU
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 38b60786d..1ec8b66f1 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 24 2011 21:05:28
-M5 revision Unknown
-M5 started Jan 24 2011 21:53:14
-M5 executing on m55-002.pool
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:38
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index 827d1ba1c..d26ecb349 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  68116                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1627972                       # Number of bytes of host memory used
-host_seconds                                  1296.92                       # Real time elapsed on the host
-host_tick_rate                               33685044                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  27953                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1692040                       # Number of bytes of host memory used
+host_seconds                                  3160.33                       # Real time elapsed on the host
+host_tick_rate                               13823537                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340674                       # Number of instructions simulated
 sim_seconds                                  0.043687                       # Number of seconds simulated
@@ -272,6 +272,8 @@ system.cpu.l2cache.total_refs                  134496                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                  120516                       # number of writebacks
 system.cpu.numCycles                         87373938                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.runCycles                         61786224                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index a73ef9125..669e84c5b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 2cca5705e..ea4e5025f 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:25:07
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 4f92cd575..553c740bc 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 227615                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215572                       # Number of bytes of host memory used
-host_seconds                                   349.68                       # Real time elapsed on the host
-host_tick_rate                               77104293                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  86589                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 236008                       # Number of bytes of host memory used
+host_seconds                                   919.19                       # Real time elapsed on the host
+host_tick_rate                               29331748                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_seconds                                  0.026962                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total     51426557                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                  88340672                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                 267754                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls          1661057                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              77942044                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                  20276638                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                   34890015                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total             52727427                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                    245061                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   242344                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           13394904                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency  9553.478677                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  6055.148214                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      1499472                       #
 system.cpu.iew.memOrderViolationEvents          20765                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       133024                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect         270323                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                112261025                       # number of integer regfile reads
+system.cpu.int_regfile_writes                55957664                       # number of integer regfile writes
 system.cpu.ipc                               1.476021                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.476021                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total     52727427                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.584713                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                  300330                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads              600062                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses       291336                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes             449677                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses               86057957                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          223986187                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses     84142849                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes          99078725                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                   89657627                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                  85452764                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                5005                       # Number of non-speculative instructions added to the IQ
@@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads          12487229                       # Nu
 system.cpu.memDep0.conflictingStores         11176863                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads             22901502                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            16112849                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                   38001                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                         53923173                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles          1782763                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       52546881                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents           52474                       # Number of times rename has blocked due to IQ full
@@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles           19225803                       # Nu
 system.cpu.rename.RENAME:SquashCycles         1300870                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles        1439133                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps           8237313                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups       444545                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    121310909                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles        77780                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts         5276                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts            3015491                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts         5274                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    143406999                       # The number of ROB reads
+system.cpu.rob.rob_writes                   194680217                       # The number of ROB writes
 system.cpu.timesIdled                           39379                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
 
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index e19472c60..d98970549 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 9be789dc3..47e63ab68 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:44:15
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:38
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 65fd7857e..1ad0b8bf6 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5477905                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 240580                       # Number of bytes of host memory used
-host_seconds                                    16.13                       # Real time elapsed on the host
-host_tick_rate                             2742055845                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1614429                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 226740                       # Number of bytes of host memory used
+host_seconds                                    54.72                       # Real time elapsed on the host
+host_tick_rate                              808136192                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.044221                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                         88442007                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                   88442007                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      8920848                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                 267757                       # Number of float alu accesses
+system.cpu.num_fp_insts                        267757                       # number of float instructions
+system.cpu.num_fp_register_reads               229023                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              227630                       # number of times the floating registers were written
+system.cpu.num_func_calls                     3321606                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         88340673                       # Number of instructions executed
-system.cpu.num_refs                          34987415                       # Number of memory references
+system.cpu.num_int_alu_accesses              78039444                       # Number of integer alu accesses
+system.cpu.num_int_insts                     78039444                       # number of integer instructions
+system.cpu.num_int_register_reads           105931758                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           52319251                       # number of times the integer registers were written
+system.cpu.num_load_insts                    20366786                       # Number of load instructions
+system.cpu.num_mem_refs                      34987415                       # number of memory refs
+system.cpu.num_store_insts                   14620629                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 0830e222d..6f171a7fa 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -157,7 +166,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index 121823232..4f3f97870 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:40:34
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 291724593..4a3fdb24c 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2249900                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 248308                       # Number of bytes of host memory used
-host_seconds                                    39.26                       # Real time elapsed on the host
-host_tick_rate                             3419804648                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 599191                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 234452                       # Number of bytes of host memory used
+host_seconds                                   147.43                       # Real time elapsed on the host
+host_tick_rate                              910763031                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.134277                       # Number of seconds simulated
@@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                  120506                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        268553976                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  268553976                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      8920848                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                 267757                       # Number of float alu accesses
+system.cpu.num_fp_insts                        267757                       # number of float instructions
+system.cpu.num_fp_register_reads               229023                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              227630                       # number of times the floating registers were written
+system.cpu.num_func_calls                     3321606                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         88340673                       # Number of instructions executed
-system.cpu.num_refs                          34987415                       # Number of memory references
+system.cpu.num_int_alu_accesses              78039444                       # Number of integer alu accesses
+system.cpu.num_int_insts                     78039444                       # number of integer instructions
+system.cpu.num_int_register_reads           105931758                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           52319251                       # number of times the integer registers were written
+system.cpu.num_load_insts                    20366786                       # Number of load instructions
+system.cpu.num_mem_refs                      34987415                       # number of memory refs
+system.cpu.num_store_insts                   14620629                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
index d32286142..2381c9471 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
index 4650e6a0c..93fbb5edc 100755
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 18 2011 03:54:36
-M5 revision 218f733923f8 7861 default qtip int/arm_gdb.patch tip
-M5 started Jan 18 2011 04:19:02
-M5 executing on aus-bc2-b9
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:24
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
index c8769189d..ca56969f4 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 156565                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 260328                       # Number of bytes of host memory used
-host_seconds                                   631.29                       # Real time elapsed on the host
-host_tick_rate                               93871242                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  60156                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 246816                       # Number of bytes of host memory used
+host_seconds                                  1643.03                       # Real time elapsed on the host
+host_tick_rate                               36067570                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    98838077                       # Number of instructions simulated
 sim_seconds                                  0.059260                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    114018884                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                  98838077                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     56                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              89710266                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                  27315295                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                   47871033                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            117533456                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       40                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           12122688                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 12759.423411                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  9476.994450                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      2833293                       #
 system.cpu.iew.memOrderViolationEvents          39532                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      1768227                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect         860228                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                255816186                       # number of integer regfile reads
+system.cpu.int_regfile_writes                78479487                       # number of integer regfile writes
 system.cpu.ipc                               0.833936                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.833936                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    117533456                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.920997                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                     187                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                 370                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           59                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                568                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              110479458                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          337237563                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    104978377                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         134232957                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  116084938                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 109156507                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded             1016199                       # Number of non-speculative instructions added to the IQ
@@ -473,7 +488,11 @@ system.cpu.memDep0.conflictingLoads           7990320                       # Nu
 system.cpu.memDep0.conflictingStores         10924699                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads             32508348                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            23389031                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               153116651                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1948149                       # number of misc regfile writes
 system.cpu.numCycles                        118519960                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles          1866194                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       74745628                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents            1883                       # Number of times rename has blocked due to IQ full
@@ -487,10 +506,14 @@ system.cpu.rename.RENAME:RunCycles           68672790                       # Nu
 system.cpu.rename.RENAME:SquashCycles         3514572                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles        1591233                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps          18613027                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups        83717                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    333328918                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles     11499162                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts       818368                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts            3724500                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts       819368                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    229794357                       # The number of ROB reads
+system.cpu.rob.rob_writes                   237655572                       # The number of ROB writes
 system.cpu.timesIdled                           60726                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 451406111..d284ed163 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -52,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
index 843c8c748..4cf2e23b7 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:44:04
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index d9333fa95..a170aadf3 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2790357                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 261760                       # Number of bytes of host memory used
-host_seconds                                    35.42                       # Real time elapsed on the host
-host_tick_rate                             1497251955                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 986864                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 237100                       # Number of bytes of host memory used
+host_seconds                                   100.15                       # Real time elapsed on the host
+host_tick_rate                              529534290                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    98838077                       # Number of instructions simulated
 sim_seconds                                  0.053035                       # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        106069965                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  106069965                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
+system.cpu.num_fp_insts                            56                       # number of float instructions
+system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         98838077                       # Number of instructions executed
-system.cpu.num_refs                          47871034                       # Number of memory references
+system.cpu.num_int_alu_accesses              89710267                       # Number of integer alu accesses
+system.cpu.num_int_insts                     89710267                       # number of integer instructions
+system.cpu.num_int_register_reads           258410605                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           73280343                       # number of times the integer registers were written
+system.cpu.num_load_insts                    27315295                       # Number of load instructions
+system.cpu.num_mem_refs                      47871034                       # number of memory refs
+system.cpu.num_store_insts                   20555739                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index 1d235cb1e..0e5c2c18c 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
index eabe42249..e391217dd 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
 hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 8e789b6bf..54e01817e 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:37:39
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 595ab3b43..b20318b2f 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 607999                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 269484                       # Number of bytes of host memory used
-host_seconds                                   161.18                       # Real time elapsed on the host
-host_tick_rate                              825650483                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 430473                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 244816                       # Number of bytes of host memory used
+host_seconds                                   227.65                       # Real time elapsed on the host
+host_tick_rate                              584574230                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    97997303                       # Number of instructions simulated
 sim_seconds                                  0.133079                       # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   88450                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        266157390                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  266157390                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
+system.cpu.num_fp_insts                            56                       # number of float instructions
+system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         97997303                       # Number of instructions executed
-system.cpu.num_refs                          47871034                       # Number of memory references
+system.cpu.num_int_alu_accesses              89710267                       # Number of integer alu accesses
+system.cpu.num_int_insts                     89710267                       # number of integer instructions
+system.cpu.num_int_register_reads           285424208                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           73333595                       # number of times the integer registers were written
+system.cpu.num_load_insts                    27315295                       # Number of load instructions
+system.cpu.num_mem_refs                      47871034                       # number of memory refs
+system.cpu.num_store_insts                   20555739                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 51965dbb5..0962890e6 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
index 27a5cc38b..7f5789393 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:33:19
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:14:11
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index b6b56aac5..d6bfda298 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1397341                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194632                       # Number of bytes of host memory used
-host_seconds                                    97.43                       # Real time elapsed on the host
-host_tick_rate                              699480350                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1204089                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 228576                       # Number of bytes of host memory used
+host_seconds                                   113.06                       # Real time elapsed on the host
+host_tick_rate                              602742669                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.068149                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                 68148678500                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        136297358                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  136297358                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
+system.cpu.num_fp_insts                       2326977                       # number of float instructions
+system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        136139203                       # Number of instructions executed
-system.cpu.num_refs                          58160249                       # Number of memory references
+system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
+system.cpu.num_int_insts                    115187758                       # number of integer instructions
+system.cpu.num_int_register_reads           263032383                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          113225733                       # number of times the integer registers were written
+system.cpu.num_load_insts                    37275868                       # Number of load instructions
+system.cpu.num_mem_refs                      58160249                       # number of memory refs
+system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 08b8aa7ee..8ec9f75ef 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index e214aaa33..b27952d03 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep 20 2010 15:04:49
-M5 revision 0c4a7d867247 7686 default qtip print-identical tip
-M5 started Sep 20 2010 16:35:02
-M5 executing on phenom
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:39
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index d33aa6f85..eb6eca0bd 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1222037                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206136                       # Number of bytes of host memory used
-host_seconds                                   111.40                       # Real time elapsed on the host
-host_tick_rate                             1821674437                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 463084                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 236284                       # Number of bytes of host memory used
+host_seconds                                   293.98                       # Real time elapsed on the host
+host_tick_rate                              690315679                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.202942                       # Number of seconds simulated
@@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   87265                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        405883984                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  405883984                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
+system.cpu.num_fp_insts                       2326977                       # number of float instructions
+system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        136139203                       # Number of instructions executed
-system.cpu.num_refs                          58160249                       # Number of memory references
+system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
+system.cpu.num_int_insts                    115187758                       # number of integer instructions
+system.cpu.num_int_register_reads           263032383                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          113225732                       # number of times the integer registers were written
+system.cpu.num_load_insts                    37275868                       # Number of load instructions
+system.cpu.num_mem_refs                      58160249                       # number of memory refs
+system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 5e62dfe3a..28a997af9 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
index b301ecfc9..d5dabed4c 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:24:57
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index aaad6352f..025b36e9a 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 148199                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206348                       # Number of bytes of host memory used
-host_seconds                                 11714.26                       # Real time elapsed on the host
-host_tick_rate                               61804258                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 163492                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 226772                       # Number of bytes of host memory used
+host_seconds                                 10618.50                       # Real time elapsed on the host
+host_tick_rate                               68182084                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_seconds                                  0.723991                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total   1347786892                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                1819780126                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                 805525                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls         16767440                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts            1718967519                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 444595663                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  605324165                       # Number of memory references committed
@@ -179,6 +182,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total           1436774330                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                       752                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      445                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses          354412327                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 35305.051302                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35462.540717                       # average ReadReq mshr miss latency
@@ -278,6 +283,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     71840083                       #
 system.cpu.iew.memOrderViolationEvents        2851639                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      3390000                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       18332236                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               3052206207                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1779704780                       # number of integer regfile writes
 system.cpu.ipc                               1.198940                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.198940                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -369,6 +376,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total   1436774330                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.592073                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                  831640                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads             1663270                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses       822278                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes             878238                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses             2317801511                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         6060328576                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses   2227662406                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        3193875126                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                 2474285485                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                2305294087                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  45                       # Number of non-speculative instructions added to the IQ
@@ -465,7 +480,11 @@ system.cpu.memDep0.conflictingLoads         123159990                       # Nu
 system.cpu.memDep0.conflictingStores         64312407                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            617102957                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           232568585                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                       1447982395                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         51393371                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1376202963                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         5887635                       # Number of times rename has blocked due to IQ full
@@ -479,10 +498,14 @@ system.cpu.rename.RENAME:RunCycles          528076479                       # Nu
 system.cpu.rename.RENAME:SquashCycles        88987438                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       27475071                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps         671478700                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups       885045                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   3534388873                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          849                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           49                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts           54007891                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           47                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   3612840225                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4916793262                       # The number of ROB writes
 system.cpu.timesIdled                          425188                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
 
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 889a2c50f..e886c5917 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 5c31e9414..56c0d3893 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:35:16
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 0e81a5825..7812c0d15 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5747960                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231948                       # Number of bytes of host memory used
-host_seconds                                   316.60                       # Real time elapsed on the host
-host_tick_rate                             2884399053                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1468260                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 218108                       # Number of bytes of host memory used
+host_seconds                                  1239.41                       # Real time elapsed on the host
+host_tick_rate                              736791940                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  0.913189                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1826378527                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1826378527                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    164021647                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                 805526                       # Number of float alu accesses
+system.cpu.num_fp_insts                        805526                       # number of float instructions
+system.cpu.num_fp_register_reads                  357                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                 345                       # number of times the floating registers were written
+system.cpu.num_func_calls                    33534877                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1819780127                       # Number of instructions executed
-system.cpu.num_refs                         611922547                       # Number of memory references
+system.cpu.num_int_alu_accesses            1725565901                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1725565901                       # number of integer instructions
+system.cpu.num_int_register_reads          2347934659                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1376202618                       # number of times the integer registers were written
+system.cpu.num_load_insts                   449492741                       # Number of load instructions
+system.cpu.num_mem_refs                     611922547                       # number of memory refs
+system.cpu.num_store_insts                  162429806                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 6c6b88ddd..6d6374beb 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -157,7 +166,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
index d211942d5..b361f245f 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:53:28
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 7c181b6aa..f893b334a 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2423488                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 239668                       # Number of bytes of host memory used
-host_seconds                                   750.89                       # Real time elapsed on the host
-host_tick_rate                             3547033530                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 590383                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 225824                       # Number of bytes of host memory used
+host_seconds                                  3082.37                       # Real time elapsed on the host
+host_tick_rate                              864089077                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  2.663444                       # Number of seconds simulated
@@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle          582065656000                       # Cy
 system.cpu.l2cache.writebacks                 1170923                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       5326887432                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 5326887432                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    164021647                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                 805526                       # Number of float alu accesses
+system.cpu.num_fp_insts                        805526                       # number of float instructions
+system.cpu.num_fp_register_reads                  357                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                 345                       # number of times the floating registers were written
+system.cpu.num_func_calls                    33534877                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1819780127                       # Number of instructions executed
-system.cpu.num_refs                         611922547                       # Number of memory references
+system.cpu.num_int_alu_accesses            1725565901                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1725565901                       # number of integer instructions
+system.cpu.num_int_register_reads          2347934659                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1376202618                       # number of times the integer registers were written
+system.cpu.num_load_insts                   449492741                       # Number of load instructions
+system.cpu.num_mem_refs                     611922547                       # number of memory refs
+system.cpu.num_store_insts                  162429806                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 3ef4a25fb..731b0df43 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
index 2f2c51bdb..e9bf20924 100755
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 03:57:47
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index ab126a693..24c1e17c3 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 165173                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 251872                       # Number of bytes of host memory used
-host_seconds                                 10349.18                       # Real time elapsed on the host
-host_tick_rate                               71148819                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 152870                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 238404                       # Number of bytes of host memory used
+host_seconds                                 11182.08                       # Real time elapsed on the host
+host_tick_rate                               65849295                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1709408682                       # Number of instructions simulated
 sim_seconds                                  0.736332                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total   1325593863                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                1709408682                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     36                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts            1523276792                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                 485926830                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  660773875                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total           1437192539                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        66                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       62                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses          305341372                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 34138.917794                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34194.369973                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores    145359637                       #
 system.cpu.iew.memOrderViolationEvents        2909115                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect     16680292                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       18278981                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               5217275964                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1582136898                       # number of integer regfile writes
 system.cpu.ipc                               1.160759                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.160759                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total   1437192539                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.426534                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                     101                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                 196                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           78                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                252                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses             2136057911                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         5702380947                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses   2009251443                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        3154359191                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                 2433961117                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                2100805548                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 422                       # Number of non-speculative instructions added to the IQ
@@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads         102861524                       # Nu
 system.cpu.memDep0.conflictingStores         93795307                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads            660629203                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           320206682                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads              3121183601                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    895                       # number of misc regfile writes
 system.cpu.numCycles                       1472664444                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles         52825853                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1347252520                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents        13396688                       # Number of times rename has blocked due to IQ full
@@ -477,10 +496,14 @@ system.cpu.rename.RENAME:RunCycles          526018927                       # Nu
 system.cpu.rename.RENAME:SquashCycles       111598676                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles       55598501                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps         598647716                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups         1008                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   7136668460                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles         9673                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts          448                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts          110186399                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts          445                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   3717337450                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4979785274                       # The number of ROB writes
 system.cpu.timesIdled                         1109854                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
 
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index 14dc84cb3..8d90d74d0 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -52,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
index 9eea795e5..1ce869a83 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:37:39
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:58:23
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 11106ff07..8d3a8d25e 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2718053                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 254288                       # Number of bytes of host memory used
-host_seconds                                   628.91                       # Real time elapsed on the host
-host_tick_rate                             1359028059                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1030645                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 229520                       # Number of bytes of host memory used
+host_seconds                                  1658.58                       # Real time elapsed on the host
+host_tick_rate                              515323054                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1709408682                       # Number of instructions simulated
 sim_seconds                                  0.854706                       # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1709411231                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 1709411231                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
+system.cpu.num_fp_insts                            36                       # number of float instructions
+system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1709408682                       # Number of instructions executed
-system.cpu.num_refs                         660773876                       # Number of memory references
+system.cpu.num_int_alu_accesses            1523276793                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1523276793                       # number of integer instructions
+system.cpu.num_int_register_reads          4636623941                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1316065665                       # number of times the integer registers were written
+system.cpu.num_load_insts                   485926830                       # Number of load instructions
+system.cpu.num_mem_refs                     660773876                       # number of memory refs
+system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
index d8eed8875..3f9e59a85 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
index eabe42249..cdafa164c 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
 hack: be nice to actually delete the event here
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
index fd7ecdb8c..ba8cd6dca 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:48:19
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 4a18c77a9..923e9c734 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 640383                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 262008                       # Number of bytes of host memory used
-host_seconds                                  2660.29                       # Real time elapsed on the host
-host_tick_rate                              913967481                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 495941                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 237232                       # Number of bytes of host memory used
+host_seconds                                  3435.10                       # Real time elapsed on the host
+host_tick_rate                              707817123                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1703605163                       # Number of instructions simulated
 sim_seconds                                  2.431420                       # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle          538044067000                       # Cy
 system.cpu.l2cache.writebacks                 1171981                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       4862840230                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 4862840230                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
+system.cpu.num_fp_insts                            36                       # number of float instructions
+system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       1703605163                       # Number of instructions executed
-system.cpu.num_refs                         660773876                       # Number of memory references
+system.cpu.num_int_alu_accesses            1523276793                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1523276793                       # number of integer instructions
+system.cpu.num_int_register_reads          5115465619                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1316065727                       # number of times the integer registers were written
+system.cpu.num_load_insts                   485926830                       # Number of load instructions
+system.cpu.num_mem_refs                     660773876                       # number of memory refs
+system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 56d944c30..89aae9c00 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -54,7 +61,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
index 2a66d5524..228e6ab0c 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:13
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 90a5205b5..a0361e843 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1732973                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 219700                       # Number of bytes of host memory used
-host_seconds                                  2704.52                       # Real time elapsed on the host
-host_tick_rate                             1052314398                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1421831                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223380                       # Number of bytes of host memory used
+host_seconds                                  3296.36                       # Real time elapsed on the host
+host_tick_rate                              863379215                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  4686862651                       # Number of instructions simulated
 sim_seconds                                  2.846007                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                2846007259500                       # N
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       5692014520                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 5692014520                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    182173305                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       4686862651                       # Number of instructions executed
-system.cpu.num_refs                        1677713086                       # Number of memory references
+system.cpu.num_int_alu_accesses            4686862580                       # Number of integer alu accesses
+system.cpu.num_int_insts                   4686862580                       # number of integer instructions
+system.cpu.num_int_register_reads         14008880122                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         4679057393                       # number of times the integer registers were written
+system.cpu.num_load_insts                  1239184749                       # Number of load instructions
+system.cpu.num_mem_refs                    1677713086                       # number of memory refs
+system.cpu.num_store_insts                  438528337                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
index c92e9f8b5..a92ea4a1d 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -154,7 +161,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
index ecac67c27..2ae184132 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:12
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index c70e9b64d..21d2dce98 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 845010                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227416                       # Number of bytes of host memory used
-host_seconds                                  5546.52                       # Real time elapsed on the host
-host_tick_rate                             1067976230                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 980837                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 231100                       # Number of bytes of host memory used
+host_seconds                                  4778.43                       # Real time elapsed on the host
+host_tick_rate                             1239642391                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  4686862651                       # Number of instructions simulated
 sim_seconds                                  5.923548                       # Number of seconds simulated
@@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle          1324806325000                       # C
 system.cpu.l2cache.writebacks                 1174631                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                      11847096156                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                11847096156                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    182173305                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       4686862651                       # Number of instructions executed
-system.cpu.num_refs                        1677713086                       # Number of memory references
+system.cpu.num_int_alu_accesses            4686862580                       # Number of integer alu accesses
+system.cpu.num_int_insts                   4686862580                       # number of integer instructions
+system.cpu.num_int_register_reads         14008880122                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         4679057393                       # number of times the integer registers were written
+system.cpu.num_load_insts                  1239184749                       # Number of load instructions
+system.cpu.num_mem_refs                    1677713086                       # number of memory refs
+system.cpu.num_store_insts                  438528337                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 389a82884..8ab14c5fa 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=InOrderCPU
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 6bea6bb9d..2bd9f8140 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 24 2011 21:05:28
-M5 revision Unknown
-M5 started Jan 24 2011 21:05:32
-M5 executing on m55-002.pool
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 81e378671..bb16b8b96 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  66004                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1421192                       # Number of bytes of host memory used
-host_seconds                                  1392.38                       # Real time elapsed on the host
-host_tick_rate                               29109416                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  25888                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1480704                       # Number of bytes of host memory used
+host_seconds                                  3550.03                       # Real time elapsed on the host
+host_tick_rate                               11417230                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903057                       # Number of instructions simulated
 sim_seconds                                  0.040531                       # Number of seconds simulated
@@ -272,6 +272,8 @@ system.cpu.l2cache.total_refs                    7072                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.numCycles                         81062947                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.runCycles                         74310489                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 02074cf40..01f3bf111 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index 6d564a58f..b9f2d3d21 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:30:09
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:48
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 6e4f9aea5..2fcd0832c 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 134338                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 210480                       # Number of bytes of host memory used
-host_seconds                                   626.63                       # Real time elapsed on the host
-host_tick_rate                               64841631                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  68515                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 230924                       # Number of bytes of host memory used
+host_seconds                                  1228.63                       # Real time elapsed on the host
+host_tick_rate                               33070698                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.040632                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total     73022923                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                  91903055                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                6862061                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls          1029620                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              79581076                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                  19996198                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                   26497301                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total             81154458                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                   6156758                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6040765                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           19059447                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 15766.588953                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11899.082569                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      4154704                       #
 system.cpu.iew.memOrderViolationEvents         268955                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       456787                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        1600647                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                137465323                       # number of integer regfile reads
+system.cpu.int_regfile_writes                75768353                       # number of integer regfile writes
 system.cpu.ipc                               1.035892                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.035892                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            7      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total     81154458                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     1.279986                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                 8012478                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads            15186691                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7058808                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes           12278263                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses               97954442                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          276254930                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses     92993062                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         174004519                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  135471680                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 104015508                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 434                       # Number of non-speculative instructions added to the IQ
@@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads          17824866                       # Nu
 system.cpu.memDep0.conflictingStores          5359806                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads             33850050                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            10655807                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                  712336                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                         81263024                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles          1835260                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       68427361                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         1124456                       # Number of times rename has blocked due to IQ full
@@ -470,10 +489,14 @@ system.cpu.rename.RENAME:RunCycles           28432140                       # Nu
 system.cpu.rename.RENAME:SquashCycles         8131535                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles        2161646                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps          47087306                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups     11932541                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    190714138                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles         5198                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts          467                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts            4785663                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts          456                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    218412469                       # The number of ROB reads
+system.cpu.rob.rob_writes                   304705559                       # The number of ROB writes
 system.cpu.timesIdled                            2403                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
 
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index a6e47a29e..1801d3968 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
index dc1519d82..06628f244 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:32:41
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:38
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index 50ef29969..3667c8fef 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4196549                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 235848                       # Number of bytes of host memory used
-host_seconds                                    21.90                       # Real time elapsed on the host
-host_tick_rate                             2098254960                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1609489                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 222008                       # Number of bytes of host memory used
+host_seconds                                    57.10                       # Real time elapsed on the host
+host_tick_rate                              804741446                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.045952                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                         91903136                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                   91903136                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      7465012                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                6862064                       # Number of float alu accesses
+system.cpu.num_fp_insts                       6862064                       # number of float instructions
+system.cpu.num_fp_register_reads              6071661                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             5851888                       # number of times the floating registers were written
+system.cpu.num_func_calls                     2059216                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         91903056                       # Number of instructions executed
-system.cpu.num_refs                          26497334                       # Number of memory references
+system.cpu.num_int_alu_accesses              79581109                       # Number of integer alu accesses
+system.cpu.num_int_insts                     79581109                       # number of integer instructions
+system.cpu.num_int_register_reads           115028592                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           62575473                       # number of times the integer registers were written
+system.cpu.num_load_insts                    19996208                       # Number of load instructions
+system.cpu.num_mem_refs                      26497334                       # number of memory refs
+system.cpu.num_store_insts                    6501126                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 92176625f..cab9a523d 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -157,7 +166,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
index 4d237e859..5503045c3 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 22:35:14
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:48
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index 90176f56c..2aaa18b18 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2386222                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 243572                       # Number of bytes of host memory used
-host_seconds                                    38.51                       # Real time elapsed on the host
-host_tick_rate                             3083013039                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 559604                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 229724                       # Number of bytes of host memory used
+host_seconds                                   164.23                       # Real time elapsed on the host
+host_tick_rate                              723015392                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.118740                       # Number of seconds simulated
@@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        237480098                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  237480098                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      7465012                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                6862064                       # Number of float alu accesses
+system.cpu.num_fp_insts                       6862064                       # number of float instructions
+system.cpu.num_fp_register_reads              6071661                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             5851888                       # number of times the floating registers were written
+system.cpu.num_func_calls                     2059216                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         91903056                       # Number of instructions executed
-system.cpu.num_refs                          26497334                       # Number of memory references
+system.cpu.num_int_alu_accesses              79581109                       # Number of integer alu accesses
+system.cpu.num_int_insts                     79581109                       # number of integer instructions
+system.cpu.num_int_register_reads           115028592                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           62575473                       # number of times the integer registers were written
+system.cpu.num_load_insts                    19996208                       # Number of load instructions
+system.cpu.num_mem_refs                      26497334                       # number of memory refs
+system.cpu.num_store_insts                    6501126                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
index 95580ac45..f95eb4d89 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
index 832370508..46dd2c791 100755
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 04:18:31
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:00:24
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
 Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav
 Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
index a8b50fb87..21ada4fbc 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  96216                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 255460                       # Number of bytes of host memory used
-host_seconds                                  1920.75                       # Real time elapsed on the host
-host_tick_rate                               78000522                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  61621                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 241964                       # Number of bytes of host memory used
+host_seconds                                  2999.07                       # Real time elapsed on the host
+host_tick_rate                               49955205                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   184806751                       # Number of instructions simulated
 sim_seconds                                  0.149819                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    285162307                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 184806751                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                1730659                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             146860811                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                  29554611                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                   42081439                       # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            299566319                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                   2799107                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2446180                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           24416320                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 25129.997165                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 21979.962430                       # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      2461724                       #
 system.cpu.iew.memOrderViolationEvents         295230                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      1407561                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       11669168                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                457836856                       # number of integer regfile reads
+system.cpu.int_regfile_writes               195349958                       # number of integer regfile writes
 system.cpu.ipc                               0.616766                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.616766                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    299566319                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.711320                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                 1965612                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads             3923910                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1824312                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes            2255873                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              212345848                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          723342864                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    197666637                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         240391153                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  220060942                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 213138842                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded             1668755                       # Number of non-speculative instructions added to the IQ
@@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads           3889323                       # Nu
 system.cpu.memDep0.conflictingStores          2640936                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads             37075609                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            14988552                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               328971278                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                4891827                       # number of misc regfile writes
 system.cpu.numCycles                        299638437                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles             3074                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      178683528                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents            2322                       # Number of times rename has blocked due to IQ full
@@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles          190277990                       # Nu
 system.cpu.rename.RENAME:SquashCycles        14404012                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles        1750038                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps          71145762                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups     14827185                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    586253105                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles     19853445                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts      2086015                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts            2928694                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts      1863087                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    506291228                       # The number of ROB reads
+system.cpu.rob.rob_writes                   457856948                       # The number of ROB writes
 system.cpu.timesIdled                            1363                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 9f4b7679d..283406dc2 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -52,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
index 4f3382663..c50fadfb0 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 19:22:41
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:35
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 45e4b8820..4a204d0cd 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2742393                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 257424                       # Number of bytes of host memory used
-host_seconds                                    68.12                       # Real time elapsed on the host
-host_tick_rate                             1499949275                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1012006                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 232796                       # Number of bytes of host memory used
+host_seconds                                   184.60                       # Real time elapsed on the host
+host_tick_rate                              553516772                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   186818826                       # Number of instructions simulated
 sim_seconds                                  0.102181                       # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        204361469                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  204361469                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
+system.cpu.num_fp_insts                       1752310                       # number of float instructions
+system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        186818826                       # Number of instructions executed
-system.cpu.num_refs                          42511846                       # Number of memory references
+system.cpu.num_int_alu_accesses             148453796                       # Number of integer alu accesses
+system.cpu.num_int_insts                    148453796                       # number of integer instructions
+system.cpu.num_int_register_reads           440904784                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          179338779                       # number of times the integer registers were written
+system.cpu.num_load_insts                    29867211                       # Number of load instructions
+system.cpu.num_mem_refs                      42511846                       # number of memory refs
+system.cpu.num_store_insts                   12644635                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
index c7e80818a..d150b1761 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
index eabe42249..83ecbdfc0 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,13 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
 hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
index 60b3eda0f..5cb7e11c7 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 19:00:18
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:24
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
index b971df920..715b30669 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 709254                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 265144                       # Number of bytes of host memory used
-host_seconds                                   262.72                       # Real time elapsed on the host
-host_tick_rate                              883179772                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 504285                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 240500                       # Number of bytes of host memory used
+host_seconds                                   369.50                       # Real time elapsed on the host
+host_tick_rate                              627947562                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   186333855                       # Number of instructions simulated
 sim_seconds                                  0.232028                       # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        464055342                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  464055342                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
+system.cpu.num_fp_insts                       1752310                       # number of float instructions
+system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        186333855                       # Number of instructions executed
-system.cpu.num_refs                          42511846                       # Number of memory references
+system.cpu.num_int_alu_accesses             148453796                       # Number of integer alu accesses
+system.cpu.num_int_insts                    148453796                       # number of integer instructions
+system.cpu.num_int_register_reads           470866018                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          179570637                       # number of times the integer registers were written
+system.cpu.num_load_insts                    29867211                       # Number of load instructions
+system.cpu.num_mem_refs                      42511846                       # number of memory refs
+system.cpu.num_store_insts                   12644635                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 1b0da48ab..c1dd735f6 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
index 30e9edddf..f4dfd8899 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:35:37
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:39
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index ec86f0831..5f3549812 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1979245                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 190260                       # Number of bytes of host memory used
-host_seconds                                    97.74                       # Real time elapsed on the host
-host_tick_rate                              989625806                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1142521                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 224208                       # Number of bytes of host memory used
+host_seconds                                   169.31                       # Real time elapsed on the host
+host_tick_rate                              571263026                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.096723                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                 96722951500                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        193445904                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  193445904                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
+system.cpu.num_fp_insts                       1970372                       # number of float instructions
+system.cpu.num_fp_register_reads              3181089                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2974850                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        193444769                       # Number of instructions executed
-system.cpu.num_refs                          76733959                       # Number of memory references
+system.cpu.num_int_alu_accesses             167974818                       # Number of integer alu accesses
+system.cpu.num_int_insts                    167974818                       # number of integer instructions
+system.cpu.num_int_register_reads           352386257                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          163703467                       # number of times the integer registers were written
+system.cpu.num_load_insts                    57735092                       # Number of load instructions
+system.cpu.num_mem_refs                      76733959                       # number of memory refs
+system.cpu.num_store_insts                   18998867                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             401                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index dc0731aa6..c8439f7fb 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,7 +161,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
index a4fbf8115..a4abb12dd 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:03:51
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:14:19
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 46f688248..f02c69451 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 953366                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216056                       # Number of bytes of host memory used
-host_seconds                                   202.91                       # Real time elapsed on the host
-host_tick_rate                             1333500122                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 498703                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 231920                       # Number of bytes of host memory used
+host_seconds                                   387.90                       # Real time elapsed on the host
+host_tick_rate                              697549821                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.270577                       # Number of seconds simulated
@@ -209,8 +209,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        541153920                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  541153920                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
+system.cpu.num_fp_insts                       1970372                       # number of float instructions
+system.cpu.num_fp_register_reads              3181089                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2974850                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        193444769                       # Number of instructions executed
-system.cpu.num_refs                          76733959                       # Number of memory references
+system.cpu.num_int_alu_accesses             167974818                       # Number of integer alu accesses
+system.cpu.num_int_insts                    167974818                       # number of integer instructions
+system.cpu.num_int_register_reads           352386257                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          163703466                       # number of times the integer registers were written
+system.cpu.num_load_insts                    57735092                       # Number of load instructions
+system.cpu.num_mem_refs                      76733959                       # number of memory refs
+system.cpu.num_store_insts                   18998867                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             401                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
index 64a0645d8..78a8cbd6c 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -481,7 +488,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
+cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
index 4773ac641..e89403a2f 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 16:34:44
-M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch
-M5 started Jan 31 2011 16:34:46
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:12
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
index daddf87eb..58c1a1259 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 118559                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 239716                       # Number of bytes of host memory used
-host_seconds                                  1867.12                       # Real time elapsed on the host
-host_tick_rate                               68319429                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  87424                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 240332                       # Number of bytes of host memory used
+host_seconds                                  2532.06                       # Real time elapsed on the host
+host_tick_rate                               50378144                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   221363017                       # Number of instructions simulated
 sim_seconds                                  0.127561                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total    243992167                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 221363017                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                2162459                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             220339606                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                  56649590                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                   77165306                       # Number of memory references committed
@@ -150,6 +153,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            254996147                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                   3212472                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2049220                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses           20440935                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 25661.556820                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 22374.875175                       # average ReadReq mshr miss latency
@@ -249,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      5084805                       #
 system.cpu.iew.memOrderViolationEvents         879354                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       151398                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        3505125                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                614135119                       # number of integer regfile reads
+system.cpu.int_regfile_writes               252115460                       # number of integer regfile writes
 system.cpu.ipc                               0.867678                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.867678                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass      1180294      0.48%      0.48% # Type of FU issued
@@ -340,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            7                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total    254996147                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.970662                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                 2542426                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads             5084249                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2387245                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes            3193021                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              243954502                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          745226741                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    239072108                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         358869082                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                  291512819                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 247636323                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                1275                       # Number of non-speculative instructions added to the IQ
@@ -420,7 +435,11 @@ system.cpu.memDep0.conflictingLoads          21807942                       # Nu
 system.cpu.memDep0.conflictingStores          4495847                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads             75869162                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            25600521                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               125958118                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
 system.cpu.numCycles                        255121086                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles          1303093                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      234363409                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         2662460                       # Number of times rename has blocked due to IQ full
@@ -433,10 +452,14 @@ system.cpu.rename.RENAME:RunCycles          180705413                       # Nu
 system.cpu.rename.RENAME:SquashCycles        11003980                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles        4387817                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps          97598616                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups      7191870                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    956102004                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles        16547                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts         1274                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts            8156807                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts         1279                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    535181849                       # The number of ROB reads
+system.cpu.rob.rob_writes                   594057529                       # The number of ROB writes
 system.cpu.timesIdled                            2349                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 4d12813eb..adbeb371c 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -54,7 +61,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
index bf0a55710..3569c883b 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:36:47
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 6fd518d60..da648dcbf 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 925477                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227168                       # Number of bytes of host memory used
-host_seconds                                   239.19                       # Real time elapsed on the host
-host_tick_rate                              549329374                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 777141                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 230844                       # Number of bytes of host memory used
+host_seconds                                   284.84                       # Real time elapsed on the host
+host_tick_rate                              461282227                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   221363018                       # Number of instructions simulated
 sim_seconds                                  0.131393                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                131393100000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        262786201                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  262786201                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      8268471                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
+system.cpu.num_fp_insts                       2162459                       # number of float instructions
+system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        221363018                       # Number of instructions executed
-system.cpu.num_refs                          77165306                       # Number of memory references
+system.cpu.num_int_alu_accesses             220339607                       # Number of integer alu accesses
+system.cpu.num_int_insts                    220339607                       # number of integer instructions
+system.cpu.num_int_register_reads           686620674                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          232532006                       # number of times the integer registers were written
+system.cpu.num_load_insts                    56649590                       # Number of load instructions
+system.cpu.num_mem_refs                      77165306                       # number of memory refs
+system.cpu.num_store_insts                   20515716                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index bf2ab6302..2709fd0f4 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -154,7 +161,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index 8e7b2eaae..31ab1843b 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:24
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index a9095b1f2..ebc389a3a 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 704710                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 234884                       # Number of bytes of host memory used
-host_seconds                                   314.12                       # Real time elapsed on the host
-host_tick_rate                              798933117                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 446836                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 238556                       # Number of bytes of host memory used
+host_seconds                                   495.40                       # Real time elapsed on the host
+host_tick_rate                              506580174                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   221363018                       # Number of instructions simulated
 sim_seconds                                  0.250961                       # Number of seconds simulated
@@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        501921262                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  501921262                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      8268471                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
+system.cpu.num_fp_insts                       2162459                       # number of float instructions
+system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                        221363018                       # Number of instructions executed
-system.cpu.num_refs                          77165306                       # Number of memory references
+system.cpu.num_int_alu_accesses             220339607                       # Number of integer alu accesses
+system.cpu.num_int_insts                    220339607                       # number of integer instructions
+system.cpu.num_int_register_reads           686620674                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          232532006                       # number of times the integer registers were written
+system.cpu.num_load_insts                    56649590                       # Number of load instructions
+system.cpu.num_mem_refs                      77165306                       # number of memory refs
+system.cpu.num_store_insts                   20515716                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 41396e67d..cc2f70a95 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=200000000
+time_sync_spin_threshold=200000
 
 [system]
 type=SparcSystem
@@ -9,27 +11,35 @@ children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_
 boot_cpu_frequency=1
 boot_osflags=a
 hypervisor_addr=1099243257856
-hypervisor_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/q_new.bin
+hypervisor_bin=/dist/m5/system/binaries/q_new.bin
 hypervisor_desc=system.hypervisor_desc
 hypervisor_desc_addr=133446500352
-hypervisor_desc_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/1up-hv.bin
+hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
 init_param=0
 kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 nvram=system.nvram
 nvram_addr=133429198848
-nvram_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/nvram1
+nvram_bin=/dist/m5/system/binaries/nvram1
 openboot_addr=1099243716608
-openboot_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/openboot_new.bin
+openboot_bin=/dist/m5/system/binaries/openboot_new.bin
 partition_desc=system.partition_desc
 partition_desc_addr=133445976064
-partition_desc_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/1up-md.bin
+partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
 physmem=system.physmem
 readfile=tests/halt.sh
 reset_addr=1099243192320
-reset_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/reset_new.bin
+reset_bin=/dist/m5/system/binaries/reset_new.bin
 rom=system.rom
 symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -110,7 +120,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/disk.s10hw2
+image_file=/dist/m5/system/disks/disk.s10hw2
 read_only=true
 
 [system.hypervisor_desc]
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index fc75aba24..fe4ad698b 100755
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:38:31
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:38:45
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 02:10:38
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:10:45
+M5 executing on burrito
 command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
 info: No kernel set for full system simulation. Assuming you know what you're doing...
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index 16e4b5160..d05ca1e9f 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2688852                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 490548                       # Number of bytes of host memory used
-host_seconds                                   829.04                       # Real time elapsed on the host
-host_tick_rate                                2694420                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1272725                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 524564                       # Number of bytes of host memory used
+host_seconds                                  1751.49                       # Real time elapsed on the host
+host_tick_rate                                1275361                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
 sim_insts                                  2229160714                       # Number of instructions simulated
 sim_seconds                                  1.116889                       # Number of seconds simulated
@@ -13,7 +13,23 @@ system.cpu.kern.inst.arm                            0                       # nu
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       2233777513                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                 2233777513                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses               14608322                       # Number of float alu accesses
+system.cpu.num_fp_insts                      14608322                       # number of float instructions
+system.cpu.num_fp_register_reads             35401841                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            22917558                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                       2229160714                       # Number of instructions executed
-system.cpu.num_refs                         547951940                       # Number of memory references
+system.cpu.num_int_alu_accesses            1839325658                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1839325658                       # number of integer instructions
+system.cpu.num_int_register_reads          4304894311                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         2108336490                       # number of times the integer registers were written
+system.cpu.num_load_insts                   349807670                       # Number of load instructions
+system.cpu.num_mem_refs                     547951940                       # number of memory refs
+system.cpu.num_store_insts                  198144270                       # Number of store instructions
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 0558e754e..92b040488 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=InOrderCPU
@@ -192,7 +201,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
index 98307cd85..254c4b8b1 100755
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 24 2011 18:18:02
-M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
-M5 started Jan 24 2011 18:18:03
-M5 executing on zooks
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index be248d562..246665e32 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  36108                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 155860                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
-host_tick_rate                              125462283                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  37548                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223436                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
+host_tick_rate                              130476959                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000022                       # Number of seconds simulated
@@ -267,6 +267,8 @@ system.cpu.l2cache.total_refs                       1                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.numCycles                            44578                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.runCycles                             7154                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index da67d287f..6d12585e0 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
index 7b6a1125b..517aaa9a6 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:24:57
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 72be64488..eda10e1bd 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  10121                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203516                       # Number of bytes of host memory used
-host_seconds                                     0.63                       # Real time elapsed on the host
-host_tick_rate                               19665204                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  34686                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223912                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
+host_tick_rate                               67319594                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6386                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        12265                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      6403                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     10                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls              127                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                  6321                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      1185                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       2050                       # Number of memory references committed
@@ -169,6 +172,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                13149                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses               1774                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 35292.253521                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622                       # average ReadReq mshr miss latency
@@ -268,6 +273,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          394                       #
 system.cpu.iew.memOrderViolationEvents             63                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          303                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            125                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                    11489                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    6462                       # number of integer regfile writes
 system.cpu.ipc                               0.257230                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.257230                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            2      0.02%      0.02% # Type of FU issued
@@ -359,6 +366,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        13149                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.373520                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                   9351                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              31807                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses         8672                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             14983                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      10848                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      9273                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
@@ -450,7 +465,11 @@ system.cpu.memDep0.conflictingLoads                34                       # Nu
 system.cpu.memDep0.conflictingStores               26                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 2242                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1259                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                            24826                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              346                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           4583                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               8                       # Number of times rename has blocked due to IQ full
@@ -463,10 +482,14 @@ system.cpu.rename.RENAME:RunCycles               2180                       # Nu
 system.cpu.rename.RENAME:SquashCycles             884                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            270                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              4300                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups           17                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups        15016                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          406                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           28                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                694                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           22                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        22718                       # The number of ROB reads
+system.cpu.rob.rob_writes                       22732                       # The number of ROB writes
 system.cpu.timesIdled                             239                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index d867b793e..14af20ce8 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
index 0053084d5..b6cabe98f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:01:37
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:39
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 301281a5e..29c354685 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1228467                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 182556                       # Number of bytes of host memory used
+host_inst_rate                                 474100                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215244                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              587751371                       # Simulator tick rate (ticks/s)
+host_tick_rate                              233713954                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             6431                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                       6431                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
+system.cpu.num_fp_insts                            10                       # number of float instructions
+system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
+system.cpu.num_func_calls                         251                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_refs                              2060                       # Number of memory references
+system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2060                       # number of memory refs
+system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 3438ec60f..5053e806a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -54,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -65,6 +74,59 @@ simpoint=0
 system=system
 uid=100
 
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=12
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+buffer_size=0
+cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.cpu_ruby_ports
+transitions_per_cycle=32
+version=0
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -73,34 +135,48 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
 block_size_bytes=64
 clock=1
-debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
+no_mem_vec=false
 profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+children=dcache
+access_phys_mem=true
+dcache=system.ruby.cpu_ruby_ports.dcache
+deadlock_threshold=500000
+icache=system.ruby.cpu_ruby_ports.dcache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.cpu_ruby_ports.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
-adaptive_routing=true
+adaptive_routing=false
 buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=10000
@@ -111,6 +187,7 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
+description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 num_int_nodes=3
@@ -118,93 +195,20 @@ print_config=false
 
 [system.ruby.network.topology.ext_links0]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
 int_node=0
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-buffer_size=0
-cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
 [system.ruby.network.topology.ext_links1]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.dir_cntrl0
 int_node=1
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links1.ext_node.directory
-directory_latency=12
-memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
 [system.ruby.network.topology.int_links0]
 type=IntLink
 bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index d9b6ae533..a6219b7a9 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -18,9 +18,9 @@ topology:
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
 virtual_net_2: active, ordered
-virtual_net_3: inactive
+virtual_net_3: active, ordered
 virtual_net_4: active, ordered
-virtual_net_5: active, ordered
+virtual_net_5: inactive
 virtual_net_6: inactive
 virtual_net_7: inactive
 virtual_net_8: inactive
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/28/2010 10:15:29
+Real time: Feb/07/2011 01:47:49
 
 Profiler Stats
 --------------
@@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667
 Elapsed_time_in_hours: 0.000277778
 Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.5
-Virtual_time_in_minutes: 0.00833333
-Virtual_time_in_hours:   0.000138889
-Virtual_time_in_days:    5.78704e-06
+Virtual_time_in_seconds: 0.35
+Virtual_time_in_minutes: 0.00583333
+Virtual_time_in_hours:   9.72222e-05
+Virtual_time_in_days:    4.05093e-06
 
 Ruby_current_time: 342698
 Ruby_start_time: 0
 Ruby_cycles: 342698
 
-mbytes_resident: 34.2148
-mbytes_total: 34.2227
-resident_ratio: 1
-
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 342699 [ 342699 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
+mbytes_resident: 37.7383
+mbytes_total: 227.77
+resident_ratio: 0.165703
 
+ruby_cycles_executed: [ 342699 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -81,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average:     3 | standard deviation: 0 | 0 0 0 6734 ]
+miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+imcomplete_dir_Times: 1729
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average:     3 | standard deviation: 0 | 0 0 0 5684 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average:     3 | standard deviation: 0 | 0 0 0 458 ]
+miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average:     3 | standard deviation: 0 | 0 0 0 592 ]
+miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -115,25 +122,31 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 7357
-page_faults: 2195
+page_reclaims: 10742
+page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 64
 
 Network Stats
 -------------
 
+total_msg_count_Control: 5190 41520
+total_msg_count_Data: 5178 372816
+total_msg_count_Response_Data: 5190 373680
+total_msg_count_Writeback_Control: 5178 41424
+total_msgs: 20736 total_bytes: 829440
+
 switch_0_inlinks: 2
 switch_0_outlinks: 2
 links_utilized_percent_switch_0: 0.157486
   links_utilized_percent_switch_0_link_0: 0.0630876 bw: 640000 base_latency: 1
   links_utilized_percent_switch_0_link_1: 0.251884 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
@@ -141,10 +154,10 @@ links_utilized_percent_switch_1: 0.157661
   links_utilized_percent_switch_1_link_0: 0.0629709 bw: 640000 base_latency: 1
   links_utilized_percent_switch_1_link_1: 0.25235 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
@@ -152,66 +165,64 @@ links_utilized_percent_switch_2: 0.252117
   links_utilized_percent_switch_2_link_0: 0.25235 bw: 160000 base_latency: 1
   links_utilized_percent_switch_2_link_1: 0.251884 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1730
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1730
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+Cache Stats: system.ruby.cpu_ruby_ports.dcache
+  system.ruby.cpu_ruby_ports.dcache_total_misses: 1730
+  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1730
+  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
+  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
+  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
 
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD:   42.0231%
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST:   15.7803%
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH:   42.1965%
+  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   42.0231%
+  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   15.7803%
+  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   42.1965%
 
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode:   1730    100%
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1730 average: 6.00925 | standard deviation: 2.00058 | 0 0 0 0 861 0 0 0 869 ]
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   1730    100%
 
- --- L1Cache 0 ---
+ --- L1Cache ---
  - Event Counts -
-Load  1185
-Ifetch  6414
-Store  865
-Data  1730
-Fwd_GETX  0
-Inv  0
-Replacement  1726
-Writeback_Ack  1726
-Writeback_Nack  0
+Load [1185 ] 1185
+Ifetch [6414 ] 6414
+Store [865 ] 865
+Data [1730 ] 1730
+Fwd_GETX [0 ] 0
+Inv [0 ] 0
+Replacement [1726 ] 1726
+Writeback_Ack [1726 ] 1726
+Writeback_Nack [0 ] 0
 
  - Transitions -
-I  Load  727
-I  Ifetch  730
-I  Store  273
-I  Inv  0 <-- 
-I  Replacement  0 <-- 
+I  Load [727 ] 727
+I  Ifetch [730 ] 730
+I  Store [273 ] 273
+I  Inv [0 ] 0
+I  Replacement [0 ] 0
 
-II  Writeback_Nack  0 <-- 
+II  Writeback_Nack [0 ] 0
 
-M  Load  458
-M  Ifetch  5684
-M  Store  592
-M  Fwd_GETX  0 <-- 
-M  Inv  0 <-- 
-M  Replacement  1726
+M  Load [458 ] 458
+M  Ifetch [5684 ] 5684
+M  Store [592 ] 592
+M  Fwd_GETX [0 ] 0
+M  Inv [0 ] 0
+M  Replacement [1726 ] 1726
 
-MI  Fwd_GETX  0 <-- 
-MI  Inv  0 <-- 
-MI  Writeback_Ack  1726
-MI  Writeback_Nack  0 <-- 
+MI  Fwd_GETX [0 ] 0
+MI  Inv [0 ] 0
+MI  Writeback_Ack [1726 ] 1726
+MI  Writeback_Nack [0 ] 0
 
-MII  Fwd_GETX  0 <-- 
+MII  Fwd_GETX [0 ] 0
 
-IS  Data  1457
+IS  Data [1457 ] 1457
 
-IM  Data  273
+IM  Data [273 ] 273
 
-Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 3456
   memory_reads: 1730
   memory_writes: 1726
@@ -231,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 162  36  92  110  106  362  98  36  32  34  83  92  110  104  84  86  83  53  50  58  64  124  212  72  66  50  122  190  220  325  42  98  
 
- --- Directory 0 ---
+ --- Directory ---
  - Event Counts -
-GETX  1730
-GETS  0
-PUTX  1726
-PUTX_NotOwner  0
-DMA_READ  0
-DMA_WRITE  0
-Memory_Data  1730
-Memory_Ack  1726
+GETX [1730 ] 1730
+GETS [0 ] 0
+PUTX [1726 ] 1726
+PUTX_NotOwner [0 ] 0
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+Memory_Data [1730 ] 1730
+Memory_Ack [1726 ] 1726
 
  - Transitions -
-I  GETX  1730
-I  PUTX_NotOwner  0 <-- 
-I  DMA_READ  0 <-- 
-I  DMA_WRITE  0 <-- 
-
-M  GETX  0 <-- 
-M  PUTX  1726
-M  PUTX_NotOwner  0 <-- 
-M  DMA_READ  0 <-- 
-M  DMA_WRITE  0 <-- 
-
-M_DRD  GETX  0 <-- 
-M_DRD  PUTX  0 <-- 
-
-M_DWR  GETX  0 <-- 
-M_DWR  PUTX  0 <-- 
-
-M_DWRI  GETX  0 <-- 
-M_DWRI  Memory_Ack  0 <-- 
-
-M_DRDI  GETX  0 <-- 
-M_DRDI  Memory_Ack  0 <-- 
-
-IM  GETX  0 <-- 
-IM  GETS  0 <-- 
-IM  PUTX  0 <-- 
-IM  PUTX_NotOwner  0 <-- 
-IM  DMA_READ  0 <-- 
-IM  DMA_WRITE  0 <-- 
-IM  Memory_Data  1730
-
-MI  GETX  0 <-- 
-MI  GETS  0 <-- 
-MI  PUTX  0 <-- 
-MI  PUTX_NotOwner  0 <-- 
-MI  DMA_READ  0 <-- 
-MI  DMA_WRITE  0 <-- 
-MI  Memory_Ack  1726
-
-ID  GETX  0 <-- 
-ID  GETS  0 <-- 
-ID  PUTX  0 <-- 
-ID  PUTX_NotOwner  0 <-- 
-ID  DMA_READ  0 <-- 
-ID  DMA_WRITE  0 <-- 
-ID  Memory_Data  0 <-- 
-
-ID_W  GETX  0 <-- 
-ID_W  GETS  0 <-- 
-ID_W  PUTX  0 <-- 
-ID_W  PUTX_NotOwner  0 <-- 
-ID_W  DMA_READ  0 <-- 
-ID_W  DMA_WRITE  0 <-- 
-ID_W  Memory_Ack  0 <-- 
-
+I  GETX [1730 ] 1730
+I  PUTX_NotOwner [0 ] 0
+I  DMA_READ [0 ] 0
+I  DMA_WRITE [0 ] 0
+
+M  GETX [0 ] 0
+M  PUTX [1726 ] 1726
+M  PUTX_NotOwner [0 ] 0
+M  DMA_READ [0 ] 0
+M  DMA_WRITE [0 ] 0
+
+M_DRD  GETX [0 ] 0
+M_DRD  PUTX [0 ] 0
+
+M_DWR  GETX [0 ] 0
+M_DWR  PUTX [0 ] 0
+
+M_DWRI  GETX [0 ] 0
+M_DWRI  Memory_Ack [0 ] 0
+
+M_DRDI  GETX [0 ] 0
+M_DRDI  Memory_Ack [0 ] 0
+
+IM  GETX [0 ] 0
+IM  GETS [0 ] 0
+IM  PUTX [0 ] 0
+IM  PUTX_NotOwner [0 ] 0
+IM  DMA_READ [0 ] 0
+IM  DMA_WRITE [0 ] 0
+IM  Memory_Data [1730 ] 1730
+
+MI  GETX [0 ] 0
+MI  GETS [0 ] 0
+MI  PUTX [0 ] 0
+MI  PUTX_NotOwner [0 ] 0
+MI  DMA_READ [0 ] 0
+MI  DMA_WRITE [0 ] 0
+MI  Memory_Ack [1726 ] 1726
+
+ID  GETX [0 ] 0
+ID  GETS [0 ] 0
+ID  PUTX [0 ] 0
+ID  PUTX_NotOwner [0 ] 0
+ID  DMA_READ [0 ] 0
+ID  DMA_WRITE [0 ] 0
+ID  Memory_Data [0 ] 0
+
+ID_W  GETX [0 ] 0
+ID_W  GETS [0 ] 0
+ID_W  PUTX [0 ] 0
+ID_W  PUTX_NotOwner [0 ] 0
+ID_W  DMA_READ [0 ] 0
+ID_W  DMA_WRITE [0 ] 0
+ID_W  Memory_Ack
\ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index b8009485a..6867d8c8b 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 27 2010 22:23:20
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 10:15:28
-M5 executing on svvint07
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:48
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index d59a173b9..a6f61bb79 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  19405                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215700                       # Number of bytes of host memory used
-host_seconds                                     0.33                       # Real time elapsed on the host
-host_tick_rate                                1038428                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  16267                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 233240                       # Number of bytes of host memory used
+host_seconds                                     0.39                       # Real time elapsed on the host
+host_tick_rate                                 870027                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000343                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           342698                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                     342698                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
+system.cpu.num_fp_insts                            10                       # number of float instructions
+system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
+system.cpu.num_func_calls                         251                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_refs                              2060                       # Number of memory references
+system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2060                       # number of memory refs
+system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 17f796bc5..8ac220e1e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
index 2df06d2e2..6e929844e 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:59:22
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 0a6e1d861..710a7cdd2 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 332796                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204128                       # Number of bytes of host memory used
+host_inst_rate                                 267933                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 222956                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1691799077                       # Simulator tick rate (ticks/s)
+host_tick_rate                             1366456557                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000033                       # Number of seconds simulated
@@ -227,8 +227,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            66014                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                      66014                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
+system.cpu.num_fp_insts                            10                       # number of float instructions
+system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
+system.cpu.num_func_calls                         251                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_refs                              2060                       # Number of memory references
+system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2060                       # number of memory refs
+system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 2ddfc3365..e99d2d594 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index fe2af5e09..8339eb49f 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:48:46
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:49
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 2363f1511..c17e16760 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  61982                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202420                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
-host_tick_rate                              188319059                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  33498                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 222808                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                              102057061                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2387                       # Number of instructions simulated
 sim_seconds                                  0.000007                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total         6328                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      2576                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                      6                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls               71                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                  2367                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                       415                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                        709                       # Number of memory references committed
@@ -169,6 +172,7 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                 6701                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses                782                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 36074.786325                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403                       # average ReadReq mshr miss latency
@@ -268,6 +272,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          141                       #
 system.cpu.iew.memOrderViolationEvents             13                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          109                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             55                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                     4283                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    2601                       # number of integer regfile writes
 system.cpu.ipc                               0.163482                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.163482                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -359,6 +365,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total         6701                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.248682                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                   3659                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              14008                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses         3396                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes              5997                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                       4276                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      3631                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
@@ -449,7 +463,11 @@ system.cpu.memDep0.conflictingLoads                16                       # Nu
 system.cpu.memDep0.conflictingStores               16                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                  793                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                 435                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                            14601                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles               63                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           1768                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               3                       # Number of times rename has blocked due to IQ full
@@ -462,10 +480,14 @@ system.cpu.rename.RENAME:RunCycles                901                       # Nu
 system.cpu.rename.RENAME:SquashCycles             373                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles             15                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              1713                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups           12                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups         5502                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          146                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts            8                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                 78                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts            6                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        10620                       # The number of ROB reads
+system.cpu.rob.rob_writes                        9524                       # The number of ROB writes
 system.cpu.timesIdled                             152                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index ac9cc91a1..43e841230 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
index 532375cf9..800e2e284 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 21:32:40
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index d0028e484..835697644 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 759729                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 228516                       # Number of bytes of host memory used
-host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              362937063                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 290762                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214352                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                              142079814                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             2596                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                       2596                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
+system.cpu.num_fp_insts                             6                       # number of float instructions
+system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                         140                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_refs                               717                       # Number of memory references
+system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
+system.cpu.num_int_insts                         2375                       # number of integer instructions
+system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
+system.cpu.num_load_insts                         419                       # Number of load instructions
+system.cpu.num_mem_refs                           717                       # number of memory refs
+system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 4c150fde0..71495ec84 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -54,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -65,6 +74,59 @@ simpoint=0
 system=system
 uid=100
 
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=12
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+buffer_size=0
+cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.cpu_ruby_ports
+transitions_per_cycle=32
+version=0
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -73,34 +135,48 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
 block_size_bytes=64
 clock=1
-debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
+no_mem_vec=false
 profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+children=dcache
+access_phys_mem=true
+dcache=system.ruby.cpu_ruby_ports.dcache
+deadlock_threshold=500000
+icache=system.ruby.cpu_ruby_ports.dcache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.cpu_ruby_ports.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
-adaptive_routing=true
+adaptive_routing=false
 buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=10000
@@ -111,6 +187,7 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
+description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 num_int_nodes=3
@@ -118,93 +195,20 @@ print_config=false
 
 [system.ruby.network.topology.ext_links0]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
 int_node=0
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-buffer_size=0
-cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
 [system.ruby.network.topology.ext_links1]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.dir_cntrl0
 int_node=1
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links1.ext_node.directory
-directory_latency=12
-memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
 [system.ruby.network.topology.int_links0]
 type=IntLink
 bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index edd5bdfcc..c43ead0e8 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -18,9 +18,9 @@ topology:
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
 virtual_net_2: active, ordered
-virtual_net_3: inactive
+virtual_net_3: active, ordered
 virtual_net_4: active, ordered
-virtual_net_5: active, ordered
+virtual_net_5: inactive
 virtual_net_6: inactive
 virtual_net_7: inactive
 virtual_net_8: inactive
@@ -34,40 +34,29 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/28/2010 10:26:06
+Real time: Feb/07/2011 01:47:37
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.25
-Virtual_time_in_minutes: 0.00416667
-Virtual_time_in_hours:   6.94444e-05
-Virtual_time_in_days:    2.89352e-06
+Virtual_time_in_seconds: 0.26
+Virtual_time_in_minutes: 0.00433333
+Virtual_time_in_hours:   7.22222e-05
+Virtual_time_in_days:    3.00926e-06
 
 Ruby_current_time: 123378
 Ruby_start_time: 0
 Ruby_cycles: 123378
 
-mbytes_resident: 32.8828
-mbytes_total: 32.8906
-resident_ratio: 1
-
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 123379 [ 123379 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
+mbytes_resident: 36.4062
+mbytes_total: 226.781
+resident_ratio: 0.160552
 
+ruby_cycles_executed: [ 123379 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -81,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_2: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average:     3 | standard deviation: 0 | 0 0 0 2668 ]
+miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+imcomplete_dir_Times: 625
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average:     3 | standard deviation: 0 | 0 0 0 2288 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average:     3 | standard deviation: 0 | 0 0 0 170 ]
+miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average:     3 | standard deviation: 0 | 0 0 0 210 ]
+miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -115,25 +122,31 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 7118
-page_faults: 2103
+page_reclaims: 10395
+page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 64
 
 Network Stats
 -------------
 
+total_msg_count_Control: 1878 15024
+total_msg_count_Data: 1866 134352
+total_msg_count_Response_Data: 1878 135216
+total_msg_count_Writeback_Control: 1866 14928
+total_msgs: 7488 total_bytes: 299520
+
 switch_0_inlinks: 2
 switch_0_outlinks: 2
 links_utilized_percent_switch_0: 0.157808
   links_utilized_percent_switch_0_link_0: 0.0633825 bw: 640000 base_latency: 1
   links_utilized_percent_switch_0_link_1: 0.252233 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
@@ -141,10 +154,10 @@ links_utilized_percent_switch_1: 0.158294
   links_utilized_percent_switch_1_link_0: 0.0630582 bw: 640000 base_latency: 1
   links_utilized_percent_switch_1_link_1: 0.25353 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
@@ -152,66 +165,64 @@ links_utilized_percent_switch_2: 0.252881
   links_utilized_percent_switch_2_link_0: 0.25353 bw: 160000 base_latency: 1
   links_utilized_percent_switch_2_link_1: 0.252233 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 626
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 626
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+Cache Stats: system.ruby.cpu_ruby_ports.dcache
+  system.ruby.cpu_ruby_ports.dcache_total_misses: 626
+  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 626
+  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
+  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
+  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
 
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD:   39.1374%
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST:   13.4185%
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH:   47.4441%
+  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   39.1374%
+  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   13.4185%
+  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   47.4441%
 
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode:   626    100%
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 626 average: 5.71885 | standard deviation: 1.98192 | 0 0 0 0 357 0 0 0 269 ]
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   626    100%
 
- --- L1Cache 0 ---
+ --- L1Cache ---
  - Event Counts -
-Load  415
-Ifetch  2585
-Store  294
-Data  626
-Fwd_GETX  0
-Inv  0
-Replacement  622
-Writeback_Ack  622
-Writeback_Nack  0
+Load [415 ] 415
+Ifetch [2585 ] 2585
+Store [294 ] 294
+Data [626 ] 626
+Fwd_GETX [0 ] 0
+Inv [0 ] 0
+Replacement [622 ] 622
+Writeback_Ack [622 ] 622
+Writeback_Nack [0 ] 0
 
  - Transitions -
-I  Load  245
-I  Ifetch  297
-I  Store  84
-I  Inv  0 <-- 
-I  Replacement  0 <-- 
+I  Load [245 ] 245
+I  Ifetch [297 ] 297
+I  Store [84 ] 84
+I  Inv [0 ] 0
+I  Replacement [0 ] 0
 
-II  Writeback_Nack  0 <-- 
+II  Writeback_Nack [0 ] 0
 
-M  Load  170
-M  Ifetch  2288
-M  Store  210
-M  Fwd_GETX  0 <-- 
-M  Inv  0 <-- 
-M  Replacement  622
+M  Load [170 ] 170
+M  Ifetch [2288 ] 2288
+M  Store [210 ] 210
+M  Fwd_GETX [0 ] 0
+M  Inv [0 ] 0
+M  Replacement [622 ] 622
 
-MI  Fwd_GETX  0 <-- 
-MI  Inv  0 <-- 
-MI  Writeback_Ack  622
-MI  Writeback_Nack  0 <-- 
+MI  Fwd_GETX [0 ] 0
+MI  Inv [0 ] 0
+MI  Writeback_Ack [622 ] 622
+MI  Writeback_Nack [0 ] 0
 
-MII  Fwd_GETX  0 <-- 
+MII  Fwd_GETX [0 ] 0
 
-IS  Data  542
+IS  Data [542 ] 542
 
-IM  Data  84
+IM  Data [84 ] 84
 
-Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 1248
   memory_reads: 626
   memory_writes: 622
@@ -231,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 55  40  0  100  42  42  88  45  14  10  14  10  46  82  38  6  22  14  14  48  20  52  26  92  34  10  12  24  28  44  38  138  
 
- --- Directory 0 ---
+ --- Directory ---
  - Event Counts -
-GETX  626
-GETS  0
-PUTX  622
-PUTX_NotOwner  0
-DMA_READ  0
-DMA_WRITE  0
-Memory_Data  626
-Memory_Ack  622
+GETX [626 ] 626
+GETS [0 ] 0
+PUTX [622 ] 622
+PUTX_NotOwner [0 ] 0
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+Memory_Data [626 ] 626
+Memory_Ack [622 ] 622
 
  - Transitions -
-I  GETX  626
-I  PUTX_NotOwner  0 <-- 
-I  DMA_READ  0 <-- 
-I  DMA_WRITE  0 <-- 
-
-M  GETX  0 <-- 
-M  PUTX  622
-M  PUTX_NotOwner  0 <-- 
-M  DMA_READ  0 <-- 
-M  DMA_WRITE  0 <-- 
-
-M_DRD  GETX  0 <-- 
-M_DRD  PUTX  0 <-- 
-
-M_DWR  GETX  0 <-- 
-M_DWR  PUTX  0 <-- 
-
-M_DWRI  GETX  0 <-- 
-M_DWRI  Memory_Ack  0 <-- 
-
-M_DRDI  GETX  0 <-- 
-M_DRDI  Memory_Ack  0 <-- 
-
-IM  GETX  0 <-- 
-IM  GETS  0 <-- 
-IM  PUTX  0 <-- 
-IM  PUTX_NotOwner  0 <-- 
-IM  DMA_READ  0 <-- 
-IM  DMA_WRITE  0 <-- 
-IM  Memory_Data  626
-
-MI  GETX  0 <-- 
-MI  GETS  0 <-- 
-MI  PUTX  0 <-- 
-MI  PUTX_NotOwner  0 <-- 
-MI  DMA_READ  0 <-- 
-MI  DMA_WRITE  0 <-- 
-MI  Memory_Ack  622
-
-ID  GETX  0 <-- 
-ID  GETS  0 <-- 
-ID  PUTX  0 <-- 
-ID  PUTX_NotOwner  0 <-- 
-ID  DMA_READ  0 <-- 
-ID  DMA_WRITE  0 <-- 
-ID  Memory_Data  0 <-- 
-
-ID_W  GETX  0 <-- 
-ID_W  GETS  0 <-- 
-ID_W  PUTX  0 <-- 
-ID_W  PUTX_NotOwner  0 <-- 
-ID_W  DMA_READ  0 <-- 
-ID_W  DMA_WRITE  0 <-- 
-ID_W  Memory_Ack  0 <-- 
-
+I  GETX [626 ] 626
+I  PUTX_NotOwner [0 ] 0
+I  DMA_READ [0 ] 0
+I  DMA_WRITE [0 ] 0
+
+M  GETX [0 ] 0
+M  PUTX [622 ] 622
+M  PUTX_NotOwner [0 ] 0
+M  DMA_READ [0 ] 0
+M  DMA_WRITE [0 ] 0
+
+M_DRD  GETX [0 ] 0
+M_DRD  PUTX [0 ] 0
+
+M_DWR  GETX [0 ] 0
+M_DWR  PUTX [0 ] 0
+
+M_DWRI  GETX [0 ] 0
+M_DWRI  Memory_Ack [0 ] 0
+
+M_DRDI  GETX [0 ] 0
+M_DRDI  Memory_Ack [0 ] 0
+
+IM  GETX [0 ] 0
+IM  GETS [0 ] 0
+IM  PUTX [0 ] 0
+IM  PUTX_NotOwner [0 ] 0
+IM  DMA_READ [0 ] 0
+IM  DMA_WRITE [0 ] 0
+IM  Memory_Data [626 ] 626
+
+MI  GETX [0 ] 0
+MI  GETS [0 ] 0
+MI  PUTX [0 ] 0
+MI  PUTX_NotOwner [0 ] 0
+MI  DMA_READ [0 ] 0
+MI  DMA_WRITE [0 ] 0
+MI  Memory_Ack [622 ] 622
+
+ID  GETX [0 ] 0
+ID  GETS [0 ] 0
+ID  PUTX [0 ] 0
+ID  PUTX_NotOwner [0 ] 0
+ID  DMA_READ [0 ] 0
+ID  DMA_WRITE [0 ] 0
+ID  Memory_Data [0 ] 0
+
+ID_W  GETX [0 ] 0
+ID_W  GETS [0 ] 0
+ID_W  PUTX [0 ] 0
+ID_W  PUTX_NotOwner [0 ] 0
+ID_W  DMA_READ [0 ] 0
+ID_W  DMA_WRITE [0 ] 0
+ID_W  Memory_Ack
\ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 994f7ec2d..5f04faac1 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 27 2010 22:23:20
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 10:26:06
-M5 executing on svvint07
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:36
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index dd60f4239..8d615ceb9 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  51538                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214632                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                                2467461                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  17883                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 232228                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
+host_tick_rate                                 854675                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000123                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           123378                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                     123378                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
+system.cpu.num_fp_insts                             6                       # number of float instructions
+system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                         140                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_refs                               717                       # Number of memory references
+system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
+system.cpu.num_int_insts                         2375                       # number of integer instructions
+system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
+system.cpu.num_load_insts                         419                       # Number of load instructions
+system.cpu.num_mem_refs                           717                       # number of memory refs
+system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index c142fa659..6019fe73e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index 6dd6e994b..37ac69d98 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:52:05
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:36
+M5 executing on burrito
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index f08ca087e..aa9ef9160 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  97740                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203308                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-host_tick_rate                              629585132                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 236465                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 222144                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                             1500776387                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000017                       # Number of seconds simulated
@@ -226,8 +226,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            33538                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                      33538                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
+system.cpu.num_fp_insts                             6                       # number of float instructions
+system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                         140                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_refs                               717                       # Number of memory references
+system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
+system.cpu.num_int_insts                         2375                       # number of integer instructions
+system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
+system.cpu.num_load_insts                         419                       # Number of load instructions
+system.cpu.num_mem_refs                           717                       # number of memory refs
+system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
index 9981924d0..b3ae554b5 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
index 898cae0a1..8fbed30cd 100755
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 04:32:17
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:58:16
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
index dbec33d6c..d630e1a83 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  59213                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 247916                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-host_tick_rate                              108401013                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  29952                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 234448                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
+host_tick_rate                               54904580                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5620                       # Number of instructions simulated
 sim_seconds                                  0.000010                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        10656                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      5620                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                  4889                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      1207                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       2145                       # Number of memory references committed
@@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                11818                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses               1675                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 34635.549872                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 33596.573209                       # average ReadReq mshr miss latency
@@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          708                       #
 system.cpu.iew.memOrderViolationEvents             34                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          609                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             33                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                    19236                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5710                       # number of integer regfile writes
 system.cpu.ipc                               0.272340                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.272340                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        11818                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.440202                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  54                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                 58                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                   9243                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              30172                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses         7972                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             17831                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      11904                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      9084                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                   2                       # Number of non-speculative instructions added to the IQ
@@ -458,7 +472,11 @@ system.cpu.memDep0.conflictingLoads                12                       # Nu
 system.cpu.memDep0.conflictingStores               11                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 2545                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1646                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                   15396                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      3                       # number of misc regfile writes
 system.cpu.numCycles                            20636                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              346                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           4006                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents              46                       # Number of times rename has blocked due to IQ full
@@ -471,10 +489,14 @@ system.cpu.rename.RENAME:RunCycles               2314                       # Nu
 system.cpu.rename.RENAME:SquashCycles            1162                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            187                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              6085                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups          744                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups        36764                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          271                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts            4                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                537                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts            1                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        22070                       # The number of ROB reads
+system.cpu.rob.rob_writes                       24470                       # The number of ROB writes
 system.cpu.timesIdled                             180                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
index 0aafa817f..327106c53 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
index 7deff62bb..301661eda 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:37:39
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 415af9a3d..25bd032b8 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 402550                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 249936                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              197047093                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 100802                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 225720                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                               50271986                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5620                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             5633                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                       5633                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5620                       # Number of instructions executed
-system.cpu.num_refs                              2145                       # Number of memory references
+system.cpu.num_int_alu_accesses                  4889                       # Number of integer alu accesses
+system.cpu.num_int_insts                         4889                       # number of integer instructions
+system.cpu.num_int_register_reads               14091                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3689                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1207                       # Number of load instructions
+system.cpu.num_mem_refs                          2145                       # number of memory refs
+system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
index d4111deef..d0bdfed8e 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -157,7 +166,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
index a1f858063..de21768b5 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  7 2010 18:51:32
-M5 revision 331c8c76d885 7806 default qtip tip ext/mismatched_new_delete.patch
-M5 started Dec  7 2010 18:51:46
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:58:13
+M5 executing on burrito
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
index 3c0d4e2a6..438991f53 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 315416                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 248988                       # Number of bytes of host memory used
+host_inst_rate                                 265936                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 233432                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1472008046                       # Simulator tick rate (ticks/s)
+host_tick_rate                             1242220035                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5563                       # Number of instructions simulated
 sim_seconds                                  0.000026                       # Number of seconds simulated
@@ -237,8 +237,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            52692                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                      52692                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5563                       # Number of instructions executed
-system.cpu.num_refs                              2145                       # Number of memory references
+system.cpu.num_int_alu_accesses                  4889                       # Number of integer alu accesses
+system.cpu.num_int_insts                         4889                       # number of integer instructions
+system.cpu.num_int_register_reads               15212                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3689                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1207                       # Number of load instructions
+system.cpu.num_mem_refs                          2145                       # number of memory refs
+system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
index d479ef8bf..5ba5eb09f 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=InOrderCPU
@@ -246,7 +255,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
index dc388ddae..2ad70ea48 100755
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 24 2011 18:37:16
-M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
-M5 started Jan 24 2011 18:37:18
-M5 executing on zooks
+M5 compiled Feb  7 2011 01:55:51
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:02
+M5 executing on burrito
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 170c01854..1e86aa862 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  32637                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 156860                       # Number of bytes of host memory used
+host_inst_rate                                  32668                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 224608                       # Number of bytes of host memory used
 host_seconds                                     0.18                       # Real time elapsed on the host
-host_tick_rate                              120410651                       # Simulator tick rate (ticks/s)
+host_tick_rate                              120542676                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000022                       # Number of seconds simulated
@@ -253,6 +253,8 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.numCycles                            43069                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.runCycles                             6002                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
index a9c72ed3e..a58be5b4d 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
index 6b2281542..5ff276ac0 100755
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 21:17:36
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 21:17:39
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:55:51
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:01
+M5 executing on burrito
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
index a5f35787b..7a8012ce7 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  35741                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204488                       # Number of bytes of host memory used
+host_inst_rate                                  37179                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 224748                       # Number of bytes of host memory used
 host_seconds                                     0.14                       # Real time elapsed on the host
-host_tick_rate                               88262097                       # Simulator tick rate (ticks/s)
+host_tick_rate                               91756799                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5169                       # Number of instructions simulated
 sim_seconds                                  0.000013                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        12273                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      5826                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                      2                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls               87                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                  5124                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      1164                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       2089                       # Number of memory references committed
@@ -162,6 +165,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                12922                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses               1555                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 36274.074074                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109                       # average ReadReq mshr miss latency
@@ -261,6 +266,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          210                       #
 system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          259                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            118                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                     9780                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    4751                       # number of integer regfile writes
 system.cpu.ipc                               0.202151                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.202151                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -352,6 +359,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        12922                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.288346                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                   7513                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              27837                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses         6791                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             10538                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                       8058                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      7373                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  11                       # Number of non-speculative instructions added to the IQ
@@ -436,7 +451,10 @@ system.cpu.memDep0.conflictingLoads                 5                       # Nu
 system.cpu.memDep0.conflictingStores                1                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 2139                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1135                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                     136                       # number of misc regfile reads
 system.cpu.numCycles                            25570                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              238                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           3410                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IdleCycles              8931                       # Number of cycles rename is idle
@@ -448,10 +466,14 @@ system.cpu.rename.RENAME:RunCycles               2609                       # Nu
 system.cpu.rename.RENAME:SquashCycles             649                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles             81                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              2709                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups            5                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups        12083                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          414                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           16                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                196                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           11                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        21491                       # The number of ROB reads
+system.cpu.rob.rob_writes                       19268                       # The number of ROB writes
 system.cpu.timesIdled                             259                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 6242699da..8a615b31d 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -111,7 +120,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index 5dbd10419..931c89646 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2010 23:13:04
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:11:22
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 01:55:51
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:01
+M5 executing on burrito
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index a6694501e..d5304c4b4 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1101929                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 183300                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              525428314                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 106820                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 216064                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                               53148750                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -29,8 +29,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             5828                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                       5828                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
+system.cpu.num_fp_insts                             2                       # number of float instructions
+system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
+system.cpu.num_func_calls                         194                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5827                       # Number of instructions executed
-system.cpu.num_refs                              2090                       # Number of memory references
+system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
+system.cpu.num_int_insts                         5126                       # number of integer instructions
+system.cpu.num_int_register_reads                7301                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1164                       # Number of load instructions
+system.cpu.num_mem_refs                          2090                       # number of memory refs
+system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index b37edc581..15d83d7b2 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu physmem ruby
-mem_mode=atomic
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -86,8 +95,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
 
 [system.cpu.dtb]
 type=MipsTLB
@@ -108,7 +117,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -119,6 +128,59 @@ simpoint=0
 system=system
 uid=100
 
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=12
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+buffer_size=0
+cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.cpu_ruby_ports
+transitions_per_cycle=32
+version=0
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -127,35 +189,48 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
 block_size_bytes=64
 clock=1
-debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
+no_mem_vec=false
 profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tech_nm=45
 tracer=system.ruby.tracer
 
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+children=dcache
+access_phys_mem=true
+dcache=system.ruby.cpu_ruby_ports.dcache
+deadlock_threshold=500000
+icache=system.ruby.cpu_ruby_ports.dcache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.cpu_ruby_ports.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
-adaptive_routing=true
+adaptive_routing=false
 buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=10000
@@ -166,6 +241,7 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
+description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 num_int_nodes=3
@@ -173,93 +249,20 @@ print_config=false
 
 [system.ruby.network.topology.ext_links0]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
 int_node=0
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-buffer_size=0
-cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
 [system.ruby.network.topology.ext_links1]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.dir_cntrl0
 int_node=1
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links1.ext_node.directory
-directory_latency=12
-memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
 [system.ruby.network.topology.int_links0]
 type=IntLink
 bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
index 87d5c1036..4a1640a47 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 21 2010 11:12:15
-M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
-M5 started Jan 21 2010 11:12:51
-M5 executing on svvint07
+M5 compiled Feb  7 2011 01:55:51
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:00
+M5 executing on burrito
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index c0deed77b..0a46cd560 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  24278                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 347460                       # Number of bytes of host memory used
+host_inst_rate                                  24226                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 234168                       # Number of bytes of host memory used
 host_seconds                                     0.24                       # Real time elapsed on the host
-host_tick_rate                                1220626                       # Simulator tick rate (ticks/s)
+host_tick_rate                                1216878                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000293                       # Number of seconds simulated
@@ -29,8 +29,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           292960                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                     292960                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
+system.cpu.num_fp_insts                             2                       # number of float instructions
+system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
+system.cpu.num_func_calls                         194                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5827                       # Number of instructions executed
-system.cpu.num_refs                              2090                       # Number of memory references
+system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
+system.cpu.num_int_insts                         5126                       # number of integer instructions
+system.cpu.num_int_register_reads                7301                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1164                       # Number of load instructions
+system.cpu.num_mem_refs                          2090                       # number of memory refs
+system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index e2f4de6ac..01d13de53 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index bfd8a31fc..4a897b2a2 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout
-Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 12:56:28
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:56:30
-M5 executing on zizzer
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
+M5 compiled Feb  7 2011 01:55:51
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:00
+M5 executing on burrito
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index f4ea21892..27b53a7ab 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                   5098                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204896                       # Number of bytes of host memory used
-host_seconds                                     1.14                       # Real time elapsed on the host
-host_tick_rate                               28066026                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 344481                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223780                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                             1868884758                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000032                       # Number of seconds simulated
@@ -213,8 +213,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            64176                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                      64176                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
+system.cpu.num_fp_insts                             2                       # number of float instructions
+system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
+system.cpu.num_func_calls                         194                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5827                       # Number of instructions executed
-system.cpu.num_refs                              2090                       # Number of memory references
+system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
+system.cpu.num_int_insts                         5126                       # number of integer instructions
+system.cpu.num_int_register_reads                7301                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1164                       # Number of load instructions
+system.cpu.num_mem_refs                          2090                       # number of memory refs
+system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
index 3d11c96e4..195dd9e9c 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
index 29a71f392..799831583 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
@@ -1,5 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 16206088. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 42898616. This will break if not /dev/zero.
 For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
index 6bd581433..9ed661104 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 17:18:01
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 17:18:03
-M5 executing on zizzer
+M5 compiled Feb  7 2011 02:06:34
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:06:41
+M5 executing on burrito
 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
index 8b311d8d3..eed636458 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  12762                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202140                       # Number of bytes of host memory used
-host_seconds                                     0.45                       # Real time elapsed on the host
-host_tick_rate                               25804848                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  32835                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 222408                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
+host_tick_rate                               66311402                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5800                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        10473                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      5800                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     22                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls              103                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                  5706                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                       962                       # Number of loads committed
 system.cpu.commit.COM:membars                       7                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       2008                       # Number of memory references committed
@@ -162,6 +165,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                11043                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses               1490                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 36422.279793                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434                       # average ReadReq mshr miss latency
@@ -261,6 +266,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          404                       #
 system.cpu.iew.memOrderViolationEvents             42                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          201                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             76                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                    12419                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    6594                       # number of integer regfile writes
 system.cpu.ipc                               0.247156                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.247156                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -352,6 +359,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        11043                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.344697                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      31                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  59                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                   8211                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              27329                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses         7555                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             12158                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                       9163                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      8089                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  22                       # Number of non-speculative instructions added to the IQ
@@ -437,6 +452,8 @@ system.cpu.memDep0.conflictingStores               29                       # Nu
 system.cpu.memDep0.insertedLoads                 1681                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1450                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                            23467                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              312                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           5007                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               7                       # Number of times rename has blocked due to IQ full
@@ -449,10 +466,14 @@ system.cpu.rename.RENAME:RunCycles               1825                       # Nu
 system.cpu.rename.RENAME:SquashCycles             570                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            243                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              3701                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups           55                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups        16177                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          337                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           22                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                473                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           22                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        19611                       # The number of ROB reads
+system.cpu.rob.rob_writes                       18950                       # The number of ROB writes
 system.cpu.timesIdled                             230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls               9                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
index 1ef6f51da..c4bee2b32 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -58,7 +67,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
index a2a4d88c2..4e7b25b97 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
@@ -1,5 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 13074680. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 39589752. This will break if not /dev/zero.
 For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
index 23b972156..dea57bc4d 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2010 23:13:07
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 24 2010 23:13:11
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 02:06:34
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:06:40
+M5 executing on burrito
 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
index 8c0754d0c..1731c3473 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 277162                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 181156                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                              136566988                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 628022                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214048                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                              304927994                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5801                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -29,8 +29,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             5801                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                       5801                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          896                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     22                       # Number of float alu accesses
+system.cpu.num_fp_insts                            22                       # number of float instructions
+system.cpu.num_fp_register_reads                   20                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
+system.cpu.num_func_calls                         200                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5801                       # Number of instructions executed
-system.cpu.num_refs                              2008                       # Number of memory references
+system.cpu.num_int_alu_accesses                  5706                       # Number of integer alu accesses
+system.cpu.num_int_insts                         5706                       # number of integer instructions
+system.cpu.num_int_register_reads                9541                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               5005                       # number of times the integer registers were written
+system.cpu.num_load_insts                         962                       # Number of load instructions
+system.cpu.num_mem_refs                          2008                       # number of memory refs
+system.cpu.num_store_insts                       1046                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls               9                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index de14f79c7..fe9f8a548 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
index ec097652e..38db96c18 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:37:59
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:14:08
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index 01cd0d37d..2caa46c35 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 897027                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 182692                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              434663663                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  96674                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215848                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                               48656953                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                     2701000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             5403                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                       5403                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5340                       # Number of instructions executed
-system.cpu.num_refs                              1402                       # Number of memory references
+system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
+system.cpu.num_int_insts                         4517                       # number of integer instructions
+system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4859                       # number of times the integer registers were written
+system.cpu.num_load_insts                         724                       # Number of load instructions
+system.cpu.num_mem_refs                          1402                       # number of memory refs
+system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index eb5199f6d..6590fce9b 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu physmem ruby
-mem_mode=atomic
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -54,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -65,6 +74,59 @@ simpoint=0
 system=system
 uid=100
 
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=12
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+buffer_size=0
+cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.cpu_ruby_ports
+transitions_per_cycle=32
+version=0
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -73,35 +135,48 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
 block_size_bytes=64
 clock=1
-debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
+no_mem_vec=false
 profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tech_nm=45
 tracer=system.ruby.tracer
 
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+children=dcache
+access_phys_mem=true
+dcache=system.ruby.cpu_ruby_ports.dcache
+deadlock_threshold=500000
+icache=system.ruby.cpu_ruby_ports.dcache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.cpu_ruby_ports.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
-adaptive_routing=true
+adaptive_routing=false
 buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=10000
@@ -112,6 +187,7 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
+description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 num_int_nodes=3
@@ -119,93 +195,20 @@ print_config=false
 
 [system.ruby.network.topology.ext_links0]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
 int_node=0
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-buffer_size=0
-cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
 [system.ruby.network.topology.ext_links1]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.dir_cntrl0
 int_node=1
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links1.ext_node.directory
-directory_latency=12
-memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
 [system.ruby.network.topology.int_links0]
 type=IntLink
 bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index 2464ac2ec..b11f8c789 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -4,16 +4,11 @@
 RubySystem config:
   random_seed: 1234
   randomization: 0
-  tech_nm: 45
   cycle_period: 1
   block_size_bytes: 64
   block_size_bits: 6
   memory_size_bytes: 134217728
   memory_size_bits: 27
-DirectoryMemory Global Config: 
-  number of directory memories: 1
-  total memory size bytes: 134217728
-  total memory size bits: 27
 
 Network Configuration
 ---------------------
@@ -23,9 +18,9 @@ topology:
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
 virtual_net_2: active, ordered
-virtual_net_3: inactive
+virtual_net_3: active, ordered
 virtual_net_4: active, ordered
-virtual_net_5: active, ordered
+virtual_net_5: inactive
 virtual_net_6: inactive
 virtual_net_7: inactive
 virtual_net_8: inactive
@@ -39,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/21/2010 11:30:49
+Real time: Feb/07/2011 02:13:39
 
 Profiler Stats
 --------------
@@ -48,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667
 Elapsed_time_in_hours: 0.000277778
 Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.28
-Virtual_time_in_minutes: 0.00466667
-Virtual_time_in_hours:   7.77778e-05
-Virtual_time_in_days:    3.24074e-06
+Virtual_time_in_seconds: 0.34
+Virtual_time_in_minutes: 0.00566667
+Virtual_time_in_hours:   9.44444e-05
+Virtual_time_in_days:    3.93519e-06
 
 Ruby_current_time: 253364
 Ruby_start_time: 0
 Ruby_cycles: 253364
 
-mbytes_resident: 34.3555
-mbytes_total: 34.5312
-resident_ratio: 0.995136
-
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 253365 [ 253365 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
+mbytes_resident: 37.8555
+mbytes_total: 228.355
+resident_ratio: 0.165791
 
+ruby_cycles_executed: [ 253365 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -86,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_1: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_L1Cache: [binsize: 1 max: 3 count: 5483 average:     3 | standard deviation: 0 | 0 0 0 5483 ]
+miss_latency_Directory: [binsize: 2 max: 371 count: 1289 average: 178.544 | standard deviation: 22.1923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+imcomplete_dir_Times: 1288
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average:     3 | standard deviation: 0 | 0 0 0 4668 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 321 average:     3 | standard deviation: 0 | 0 0 0 321 ]
+miss_latency_LD_Directory: [binsize: 2 max: 285 count: 395 average: 176.514 | standard deviation: 18.6332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average:     3 | standard deviation: 0 | 0 0 0 494 ]
+miss_latency_ST_Directory: [binsize: 2 max: 371 count: 179 average: 181.905 | standard deviation: 28.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -120,25 +122,31 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 7494
-page_faults: 2200
+page_reclaims: 11225
+page_faults: 3
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1280
+block_outputs: 64
 
 Network Stats
 -------------
 
+total_msg_count_Control: 3867 30936
+total_msg_count_Data: 3855 277560
+total_msg_count_Response_Data: 3867 278424
+total_msg_count_Writeback_Control: 3855 30840
+total_msgs: 15444 total_bytes: 617760
+
 switch_0_inlinks: 2
 switch_0_outlinks: 2
 links_utilized_percent_switch_0: 0.158621
   links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1
   links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
@@ -146,10 +154,10 @@ links_utilized_percent_switch_1: 0.158857
   links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1
   links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
@@ -157,63 +165,64 @@ links_utilized_percent_switch_2: 0.253982
   links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1
   links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1289
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1289
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+Cache Stats: system.ruby.cpu_ruby_ports.dcache
+  system.ruby.cpu_ruby_ports.dcache_total_misses: 1289
+  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1289
+  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
+  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
+  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
 
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD:   30.6439%
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST:   13.8867%
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH:   55.4694%
+  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   30.6439%
+  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   13.8867%
+  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   55.4694%
 
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode:   1289    100%
-  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1289 average: 5.1249 | standard deviation: 2.01759 | 0 50 2 0 836 0 0 0 401 ]
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   1289    100%
 
- --- L1Cache 0 ---
+ --- L1Cache ---
  - Event Counts -
-Load  716
-Ifetch  5383
-Store  673
-Data  1289
-Fwd_GETX  0
-Inv  0
-Replacement  1285
-Writeback_Ack  1285
-Writeback_Nack  0
+Load [716 ] 716
+Ifetch [5383 ] 5383
+Store [673 ] 673
+Data [1289 ] 1289
+Fwd_GETX [0 ] 0
+Inv [0 ] 0
+Replacement [1285 ] 1285
+Writeback_Ack [1285 ] 1285
+Writeback_Nack [0 ] 0
 
  - Transitions -
-I  Load  395
-I  Ifetch  715
-I  Store  179
-I  Inv  0 <-- 
-I  Replacement  0 <-- 
+I  Load [395 ] 395
+I  Ifetch [715 ] 715
+I  Store [179 ] 179
+I  Inv [0 ] 0
+I  Replacement [0 ] 0
+
+II  Writeback_Nack [0 ] 0
 
-II  Writeback_Nack  0 <-- 
+M  Load [321 ] 321
+M  Ifetch [4668 ] 4668
+M  Store [494 ] 494
+M  Fwd_GETX [0 ] 0
+M  Inv [0 ] 0
+M  Replacement [1285 ] 1285
 
-M  Load  321
-M  Ifetch  4668
-M  Store  494
-M  Fwd_GETX  0 <-- 
-M  Inv  0 <-- 
-M  Replacement  1285
+MI  Fwd_GETX [0 ] 0
+MI  Inv [0 ] 0
+MI  Writeback_Ack [1285 ] 1285
+MI  Writeback_Nack [0 ] 0
 
-MI  Fwd_GETX  0 <-- 
-MI  Inv  0 <-- 
-MI  Writeback_Ack  1285
+MII  Fwd_GETX [0 ] 0
 
-IS  Data  1110
+IS  Data [1110 ] 1110
 
-IM  Data  179
+IM  Data [179 ] 179
 
-Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 2574
   memory_reads: 1289
   memory_writes: 1285
@@ -233,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 166  40  36  48  109  42  63  241  50  34  16  26  60  64  38  46  30  88  202  144  40  58  22  20  60  120  136  125  84  134  166  66  
 
- --- Directory 0 ---
+ --- Directory ---
  - Event Counts -
-GETX  1289
-GETS  0
-PUTX  1285
-PUTX_NotOwner  0
-DMA_READ  0
-DMA_WRITE  0
-Memory_Data  1289
-Memory_Ack  1285
+GETX [1289 ] 1289
+GETS [0 ] 0
+PUTX [1285 ] 1285
+PUTX_NotOwner [0 ] 0
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+Memory_Data [1289 ] 1289
+Memory_Ack [1285 ] 1285
 
  - Transitions -
-I  GETX  1289
-I  PUTX_NotOwner  0 <-- 
-I  DMA_READ  0 <-- 
-I  DMA_WRITE  0 <-- 
-
-M  GETX  0 <-- 
-M  PUTX  1285
-M  PUTX_NotOwner  0 <-- 
-M  DMA_READ  0 <-- 
-M  DMA_WRITE  0 <-- 
-
-M_DRD  GETX  0 <-- 
-M_DRD  PUTX  0 <-- 
-
-M_DWR  GETX  0 <-- 
-M_DWR  PUTX  0 <-- 
-
-M_DWRI  GETX  0 <-- 
-M_DWRI  Memory_Ack  0 <-- 
-
-M_DRDI  GETX  0 <-- 
-M_DRDI  Memory_Ack  0 <-- 
-
-IM  GETX  0 <-- 
-IM  GETS  0 <-- 
-IM  PUTX  0 <-- 
-IM  PUTX_NotOwner  0 <-- 
-IM  DMA_READ  0 <-- 
-IM  DMA_WRITE  0 <-- 
-IM  Memory_Data  1289
-
-MI  GETX  0 <-- 
-MI  GETS  0 <-- 
-MI  PUTX  0 <-- 
-MI  PUTX_NotOwner  0 <-- 
-MI  DMA_READ  0 <-- 
-MI  DMA_WRITE  0 <-- 
-MI  Memory_Ack  1285
-
-ID  GETX  0 <-- 
-ID  GETS  0 <-- 
-ID  PUTX  0 <-- 
-ID  PUTX_NotOwner  0 <-- 
-ID  DMA_READ  0 <-- 
-ID  DMA_WRITE  0 <-- 
-ID  Memory_Data  0 <-- 
-
-ID_W  GETX  0 <-- 
-ID_W  GETS  0 <-- 
-ID_W  PUTX  0 <-- 
-ID_W  PUTX_NotOwner  0 <-- 
-ID_W  DMA_READ  0 <-- 
-ID_W  DMA_WRITE  0 <-- 
-ID_W  Memory_Ack  0 <-- 
-
+I  GETX [1289 ] 1289
+I  PUTX_NotOwner [0 ] 0
+I  DMA_READ [0 ] 0
+I  DMA_WRITE [0 ] 0
+
+M  GETX [0 ] 0
+M  PUTX [1285 ] 1285
+M  PUTX_NotOwner [0 ] 0
+M  DMA_READ [0 ] 0
+M  DMA_WRITE [0 ] 0
+
+M_DRD  GETX [0 ] 0
+M_DRD  PUTX [0 ] 0
+
+M_DWR  GETX [0 ] 0
+M_DWR  PUTX [0 ] 0
+
+M_DWRI  GETX [0 ] 0
+M_DWRI  Memory_Ack [0 ] 0
+
+M_DRDI  GETX [0 ] 0
+M_DRDI  Memory_Ack [0 ] 0
+
+IM  GETX [0 ] 0
+IM  GETS [0 ] 0
+IM  PUTX [0 ] 0
+IM  PUTX_NotOwner [0 ] 0
+IM  DMA_READ [0 ] 0
+IM  DMA_WRITE [0 ] 0
+IM  Memory_Data [1289 ] 1289
+
+MI  GETX [0 ] 0
+MI  GETS [0 ] 0
+MI  PUTX [0 ] 0
+MI  PUTX_NotOwner [0 ] 0
+MI  DMA_READ [0 ] 0
+MI  DMA_WRITE [0 ] 0
+MI  Memory_Ack [1285 ] 1285
+
+ID  GETX [0 ] 0
+ID  GETS [0 ] 0
+ID  PUTX [0 ] 0
+ID  PUTX_NotOwner [0 ] 0
+ID  DMA_READ [0 ] 0
+ID  DMA_WRITE [0 ] 0
+ID  Memory_Data [0 ] 0
+
+ID_W  GETX [0 ] 0
+ID_W  GETS [0 ] 0
+ID_W  PUTX [0 ] 0
+ID_W  PUTX_NotOwner [0 ] 0
+ID_W  DMA_READ [0 ] 0
+ID_W  DMA_WRITE [0 ] 0
+ID_W  Memory_Ack
\ No newline at end of file
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index e4e5995ba..c97aaa4c9 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 21 2010 11:29:25
-M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
-M5 started Jan 21 2010 11:30:48
-M5 executing on svvint07
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:38
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index aa77d6897..5961a0ac8 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  59331                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 347024                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
-host_tick_rate                                2815062                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  26190                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 233840                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
+host_tick_rate                                1241276                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000253                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                      253364                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           253364                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                     253364                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5340                       # Number of instructions executed
-system.cpu.num_refs                              1402                       # Number of memory references
+system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
+system.cpu.num_int_insts                         4517                       # number of integer instructions
+system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4858                       # number of times the integer registers were written
+system.cpu.num_load_insts                         724                       # Number of load instructions
+system.cpu.num_mem_refs                          1402                       # number of memory refs
+system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index 35f8386c3..d416eae87 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index 9b5f99faf..1b1015662 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:05:08
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:14:00
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 28206000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 49d0076df..d21947f29 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 369934                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207380                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             1923223783                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  87383                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223480                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                              459485360                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000028                       # Number of seconds simulated
@@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            56412                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                      56412                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5340                       # Number of instructions executed
-system.cpu.num_refs                              1402                       # Number of memory references
+system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
+system.cpu.num_int_insts                         4517                       # number of integer instructions
+system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4858                       # number of times the integer registers were written
+system.cpu.num_load_insts                         724                       # Number of load instructions
+system.cpu.num_mem_refs                          1402                       # number of memory refs
+system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
index 202d0b795..1fab00bfb 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
index 12f04436f..0767b9777 100755
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 16:34:44
-M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch
-M5 started Jan 31 2011 16:34:46
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:13
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
index 0a112c922..182e72d25 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  48300                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 226820                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
-host_tick_rate                               67673766                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  47133                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 227692                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                               66053082                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9809                       # Number of instructions simulated
 sim_seconds                                  0.000014                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        15124                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      9809                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                      0                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                  9714                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      1056                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       1990                       # Number of memory references committed
@@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                15845                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                         2                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses               1255                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 37417.543860                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674                       # average ReadReq mshr miss latency
@@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          304                       #
 system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          390                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             97                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                    25083                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   11189                       # number of integer regfile writes
 system.cpu.ipc                               0.356263                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.356263                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            3      0.02%      0.02% # Type of FU issued
@@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            6                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        15845                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.454146                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                  8                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                  12501                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              40849                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses        11816                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             16975                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      13618                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     12504                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  17                       # Number of non-speculative instructions added to the IQ
@@ -414,7 +428,10 @@ system.cpu.memDep0.conflictingLoads                 4                       # Nu
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 1535                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1238                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                    5334                       # number of misc regfile reads
 system.cpu.numCycles                            27533                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              105                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           9368                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               6                       # Number of times rename has blocked due to IQ full
@@ -427,10 +444,14 @@ system.cpu.rename.RENAME:RunCycles               8027                       # Nu
 system.cpu.rename.RENAME:SquashCycles             721                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            108                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              4419                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups           16                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups        38648                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          281                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           20                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                169                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           17                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        28728                       # The number of ROB reads
+system.cpu.rob.rob_writes                       28005                       # The number of ROB writes
 system.cpu.timesIdled                             208                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index f4bc2655d..ee37f754f 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 0a2d88a32..09f4d0b50 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:13
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 7219cd6a7..1dca11ec5 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 137874                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215488                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-host_tick_rate                               79078853                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 180423                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 219128                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                              103433649                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9810                       # Number of instructions simulated
 sim_seconds                                  0.000006                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                     5651000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            11303                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                      11303                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             9810                       # Number of instructions executed
-system.cpu.num_refs                              1990                       # Number of memory references
+system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
+system.cpu.num_int_insts                         9715                       # number of integer instructions
+system.cpu.num_int_register_reads               26194                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               9368                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1056                       # Number of load instructions
+system.cpu.num_mem_refs                          1990                       # number of memory refs
+system.cpu.num_store_insts                        934                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 5985e429a..a51884b7a 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,6 +154,7 @@ tracer=system.ruby.tracer
 [system.ruby.cpu_ruby_ports]
 type=RubySequencer
 children=dcache
+access_phys_mem=true
 dcache=system.ruby.cpu_ruby_ports.dcache
 deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.dcache
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index adfa92f7c..a12716c02 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/04/2011 03:47:05
+Real time: Feb/07/2011 02:32:13
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.19
-Virtual_time_in_minutes: 0.00316667
-Virtual_time_in_hours:   5.27778e-05
-Virtual_time_in_days:    2.19907e-06
+Virtual_time_in_seconds: 0.35
+Virtual_time_in_minutes: 0.00583333
+Virtual_time_in_hours:   9.72222e-05
+Virtual_time_in_days:    4.05093e-06
 
 Ruby_current_time: 276484
 Ruby_start_time: 0
 Ruby_cycles: 276484
 
-mbytes_resident: 38.8594
-mbytes_total: 233.992
-resident_ratio: 0.166088
+mbytes_resident: 38.6094
+mbytes_total: 231.508
+resident_ratio: 0.16679
 
 ruby_cycles_executed: [ 276485 ]
 
@@ -71,8 +71,9 @@ All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
 miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_LD: [binsize: 2 max: 293 count: 1056 average: 86.3144 | standard deviation: 89.2896 | 0 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 293 count: 1048 average: 86.792 | standard deviation: 89.333 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_RMW_Read: [binsize: 1 max: 169 count: 8 average: 23.75 | standard deviation: 58.6905 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_L1Cache: [binsize: 1 max: 3 count: 7523 average:     3 | standard deviation: 0 | 0 0 0 7523 ]
 miss_latency_Directory: [binsize: 2 max: 371 count: 1377 average: 177.934 | standard deviation: 21.7881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -87,10 +88,12 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 ave
 imcomplete_dir_Times: 1376
 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average:     3 | standard deviation: 0 | 0 0 0 6287 ]
 miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 556 average:     3 | standard deviation: 0 | 0 0 0 556 ]
-miss_latency_LD_Directory: [binsize: 2 max: 293 count: 500 average: 178.96 | standard deviation: 22.8334 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 549 average:     3 | standard deviation: 0 | 0 0 0 549 ]
+miss_latency_LD_Directory: [binsize: 2 max: 293 count: 499 average: 178.98 | standard deviation: 22.8519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average:     3 | standard deviation: 0 | 0 0 0 680 ]
 miss_latency_ST_Directory: [binsize: 2 max: 371 count: 254 average: 178.039 | standard deviation: 24.8377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average:     3 | standard deviation: 0 | 0 0 0 7 ]
+miss_latency_RMW_Read_Directory: [binsize: 1 max: 169 count: 1 average:   169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -122,7 +125,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11021
+page_reclaims: 10950
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -177,17 +180,17 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
   system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   36.3108%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   18.4459%
+  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   36.2382%
+  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   18.5185%
   system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   45.2433%
 
   system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   1377    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [1056 ] 1056
+Load [1048 ] 1048
 Ifetch [6910 ] 6910
-Store [934 ] 934
+Store [942 ] 942
 Data [1377 ] 1377
 Fwd_GETX [0 ] 0
 Inv [0 ] 0
@@ -196,17 +199,17 @@ Writeback_Ack [1373 ] 1373
 Writeback_Nack [0 ] 0
 
  - Transitions -
-I  Load [500 ] 500
+I  Load [499 ] 499
 I  Ifetch [623 ] 623
-I  Store [254 ] 254
+I  Store [255 ] 255
 I  Inv [0 ] 0
 I  Replacement [0 ] 0
 
 II  Writeback_Nack [0 ] 0
 
-M  Load [556 ] 556
+M  Load [549 ] 549
 M  Ifetch [6287 ] 6287
-M  Store [680 ] 680
+M  Store [687 ] 687
 M  Fwd_GETX [0 ] 0
 M  Inv [0 ] 0
 M  Replacement [1373 ] 1373
@@ -218,9 +221,9 @@ MI  Writeback_Nack [0 ] 0
 
 MII  Fwd_GETX [0 ] 0
 
-IS  Data [1123 ] 1123
+IS  Data [1122 ] 1122
 
-IM  Data [254 ] 254
+IM  Data [255 ] 255
 
 Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 2750
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 4e5806bd6..877c8d9b9 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  4 2011 03:47:02
-M5 revision afcc4492291f 7892 default qbase qtip rubystatupdate.patch tip
-M5 started Feb  4 2011 03:47:05
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:13
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 806c6c56a..b88df01c5 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 106685                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 239612                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
-host_tick_rate                                3002497                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  32378                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 237068                       # Number of bytes of host memory used
+host_seconds                                     0.30                       # Real time elapsed on the host
+host_tick_rate                                 911908                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        9810                       # Number of instructions simulated
 sim_seconds                                  0.000276                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                      276484                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           276484                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                     276484                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             9810                       # Number of instructions executed
-system.cpu.num_refs                              1990                       # Number of memory references
+system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
+system.cpu.num_int_insts                         9715                       # number of integer instructions
+system.cpu.num_int_register_reads               26194                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               9368                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1056                       # Number of load instructions
+system.cpu.num_mem_refs                          1990                       # number of memory refs
+system.cpu.num_store_insts                        934                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index 9743aff19..ab79b8cce 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,13 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index d7b40c980..d6afbecf0 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 31 2011 14:03:49
-M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
-M5 started Jan 31 2011 14:03:51
+M5 compiled Feb  7 2011 02:32:07
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:32:24
 M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index 519e51040..0c21882f5 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 101671                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 223168                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-host_tick_rate                              297579540                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 594010                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 226844                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                             1712507148                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9810                       # Number of instructions simulated
 sim_seconds                                  0.000029                       # Number of seconds simulated
@@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            57536                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                      57536                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             9810                       # Number of instructions executed
-system.cpu.num_refs                              1990                       # Number of memory references
+system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
+system.cpu.num_int_insts                         9715                       # number of integer instructions
+system.cpu.num_int_register_reads               26194                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               9368                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1056                       # Number of load instructions
+system.cpu.num_mem_refs                          1990                       # number of memory refs
+system.cpu.num_store_insts                        934                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index eef6bf91e..0109e92d9 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 1d43d276a..e012c16b8 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:24:57
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:39
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 561bc8cb1..816b3e660 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  10660                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204092                       # Number of bytes of host memory used
-host_seconds                                     1.20                       # Real time elapsed on the host
-host_tick_rate                               11797749                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  41761                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 224488                       # Number of bytes of host memory used
+host_seconds                                     0.31                       # Real time elapsed on the host
+host_tick_rate                               46181742                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       12773                       # Number of instructions simulated
 sim_seconds                                  0.000014                       # Number of seconds simulated
@@ -43,6 +43,15 @@ system.cpu.commit.COM:committed_per_cycle::total        22158
 system.cpu.commit.COM:count::0                   6404                       # Number of instructions committed
 system.cpu.commit.COM:count::1                   6403                       # Number of instructions committed
 system.cpu.commit.COM:count::total              12807                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts::0                  10                       # Number of committed floating point instructions.
+system.cpu.commit.COM:fp_insts::1                  10                       # Number of committed floating point instructions.
+system.cpu.commit.COM:fp_insts::total              20                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls::0           127                       # Number of function calls committed.
+system.cpu.commit.COM:function_calls::1           127                       # Number of function calls committed.
+system.cpu.commit.COM:function_calls::total          254                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts::0               6321                       # Number of committed integer instructions.
+system.cpu.commit.COM:int_insts::1               6321                       # Number of committed integer instructions.
+system.cpu.commit.COM:int_insts::total          12642                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads::0                   1185                       # Number of loads committed
 system.cpu.commit.COM:loads::1                   1185                       # Number of loads committed
 system.cpu.commit.COM:loads::total               2370                       # Number of loads committed
@@ -239,6 +248,8 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                22205                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses               3993                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency::0 35767.942584                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total 35767.942584                       # average ReadReq miss latency
@@ -424,6 +435,8 @@ system.cpu.iew.lsq.thread.1.squashedStores          367                       #
 system.cpu.iew.memOrderViolationEvents            131                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect         1010                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            260                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                    23900                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   13586                       # number of integer regfile writes
 system.cpu.ipc::0                            0.225857                       # IPC: Instructions Per Cycle
 system.cpu.ipc::1                            0.225821                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.451678                       # IPC: Total IPC of All Threads
@@ -590,6 +603,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        22205                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.703773                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                  20041                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              62207                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses        18120                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             32069                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      22957                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     19902                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  46                       # Number of non-speculative instructions added to the IQ
@@ -737,7 +758,11 @@ system.cpu.memDep1.conflictingLoads                22                       # Nu
 system.cpu.memDep1.conflictingStores                7                       # Number of conflicting stores.
 system.cpu.memDep1.insertedLoads                 2368                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep1.insertedStores                1232                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      2                       # number of misc regfile writes
 system.cpu.numCycles                            28279                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles             2728                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           9166                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               4                       # Number of times rename has blocked due to IQ full
@@ -751,10 +776,14 @@ system.cpu.rename.RENAME:RunCycles               4411                       # Nu
 system.cpu.rename.RENAME:SquashCycles            2039                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles           1326                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              9705                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups           34                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups        31597                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          679                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           50                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts               3216                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           38                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                       106394                       # The number of ROB reads
+system.cpu.rob.rob_writes                       48170                       # The number of ROB writes
 system.cpu.timesIdled                             276                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload0.PROG:num_syscalls             17                       # Number of system calls
 system.cpu.workload1.PROG:num_syscalls             17                       # Number of system calls
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 285549a9c..4c6ef2b94 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
index 7c5c285a5..a2a0eb0e5 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 21:17:52
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 21:18:06
-M5 executing on zizzer
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:49
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 5aa081cb3..7ae6650a8 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  91156                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203828                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
-host_tick_rate                              117504787                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  30834                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 224180                       # Number of bytes of host memory used
+host_seconds                                     0.47                       # Real time elapsed on the host
+host_tick_rate                               39786625                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       14449                       # Number of instructions simulated
 sim_seconds                                  0.000019                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        27579                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                     15175                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                      0                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                 12186                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      2226                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       3674                       # Number of memory references committed
@@ -251,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          477                       #
 system.cpu.iew.memOrderViolationEvents             54                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          560                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            240                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                    28146                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   15679                       # number of integer regfile writes
 system.cpu.ipc                               0.387238                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.387238                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -342,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        28740                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.483451                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                  18164                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              65024                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses        17128                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             23367                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      18671                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     18039                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 566                       # Number of non-speculative instructions added to the IQ
@@ -417,7 +430,11 @@ system.cpu.memDep0.conflictingLoads                13                       # Nu
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 3058                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1925                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                    6238                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
 system.cpu.numCycles                            37313                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              254                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps          13832                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IdleCycles             13569                       # Number of cycles rename is idle
@@ -429,10 +446,13 @@ system.cpu.rename.RENAME:RunCycles               7042                       # Nu
 system.cpu.rename.RENAME:SquashCycles            1178                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            421                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              5696                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:int_rename_lookups        40450                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles         6276                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts          617                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts               2691                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts          583                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        46980                       # The number of ROB reads
+system.cpu.rob.rob_writes                       41800                       # The number of ROB writes
 system.cpu.timesIdled                             183                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index 91a9c57a5..15ddd6551 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
index a758d34e6..d6e92afd2 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:38:01
-M5 executing on SC2B0619
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:50
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index 970d208fc..1a17f9fac 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1098364                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 182400                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              540894569                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  73199                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215552                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                               36700023                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000008                       # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks                                     7618500                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            15238                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                      15238                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                            15175                       # Number of instructions executed
-system.cpu.num_refs                              3684                       # Number of memory references
+system.cpu.num_int_alu_accesses                 12231                       # Number of integer alu accesses
+system.cpu.num_int_insts                        12231                       # number of integer instructions
+system.cpu.num_int_register_reads               29059                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              13832                       # number of times the integer registers were written
+system.cpu.num_load_insts                        2232                       # Number of load instructions
+system.cpu.num_mem_refs                          3684                       # number of memory refs
+system.cpu.num_store_insts                       1452                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 04665360b..d782c12d4 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
index 27524a121..7fbb77bf6 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:03:44
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:38
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 6c8846c5d..b8651e274 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 255958                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207264                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              701295215                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 286147                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223356                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                              784088172                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000042                       # Number of seconds simulated
@@ -197,8 +197,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            83600                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                      83600                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                            15175                       # Number of instructions executed
-system.cpu.num_refs                              3684                       # Number of memory references
+system.cpu.num_int_alu_accesses                 12231                       # Number of integer alu accesses
+system.cpu.num_int_insts                        12231                       # number of integer instructions
+system.cpu.num_int_register_reads               29059                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              13831                       # number of times the integer registers were written
+system.cpu.num_load_insts                        2232                       # Number of load instructions
+system.cpu.num_mem_refs                          3684                       # number of memory refs
+system.cpu.num_store_insts                       1452                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 26eb3724f..1712ae4de 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -1,24 +1,33 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -265,7 +274,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -285,7 +294,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -411,7 +420,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -882,7 +891,9 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
+ctrl_offset=0
 disks=system.disk0 system.disk2
+io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
index 83c71fc5c..0372a3b05 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
@@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 41c773ee0..dcb0b4c2e 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 23:00:12
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 23:09:56
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:46:17
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:46:32
+M5 executing on burrito
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
 Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 8f44fff37..55bb5b9bd 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4418519                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 326752                       # Number of bytes of host memory used
-host_seconds                                    14.29                       # Real time elapsed on the host
-host_tick_rate                           130854140423                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1669061                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 312244                       # Number of bytes of host memory used
+host_seconds                                    37.84                       # Real time elapsed on the host
+host_tick_rate                            49429698361                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_seconds                                  1.870336                       # Number of seconds simulated
@@ -305,8 +305,24 @@ system.cpu0.kern.syscall::147                       2      0.88%    100.00% # nu
 system.cpu0.kern.syscall::total                   226                       # number of syscalls executed
 system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
 system.cpu0.numCycles                      3740670933                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.num_busy_cycles              57233843.686322                       # Number of busy cycles
+system.cpu0.num_conditional_control_insts      6808233                       # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses                299810                       # Number of float alu accesses
+system.cpu0.num_fp_insts                       299810                       # number of float instructions
+system.cpu0.num_fp_register_reads              147724                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             150835                       # number of times the floating registers were written
+system.cpu0.num_func_calls                    1399585                       # number of times a function call or return occured
+system.cpu0.num_idle_cycles              3683437089.313678                       # Number of idle cycles
 system.cpu0.num_insts                        57222076                       # Number of instructions executed
-system.cpu0.num_refs                         15135515                       # Number of memory references
+system.cpu0.num_int_alu_accesses             53249924                       # Number of integer alu accesses
+system.cpu0.num_int_insts                    53249924                       # number of integer instructions
+system.cpu0.num_int_register_reads           73318596                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          39827534                       # number of times the integer registers were written
+system.cpu0.num_load_insts                    9184477                       # Number of load instructions
+system.cpu0.num_mem_refs                     15135515                       # number of memory refs
+system.cpu0.num_store_insts                   5951038                       # Number of store instructions
 system.cpu1.dcache.LoadLockedReq_accesses::0        16418                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        16418                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_hits::0        15129                       # number of LoadLockedReq hits
@@ -587,8 +603,24 @@ system.cpu1.kern.syscall::132                       2      2.00%    100.00% # nu
 system.cpu1.kern.syscall::total                   100                       # number of syscalls executed
 system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
 system.cpu1.numCycles                      3740248881                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.num_busy_cycles              5936690.922345                       # Number of busy cycles
+system.cpu1.num_conditional_control_insts       577190                       # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses                 28590                       # Number of float alu accesses
+system.cpu1.num_fp_insts                        28590                       # number of float instructions
+system.cpu1.num_fp_register_reads               17889                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              17683                       # number of times the floating registers were written
+system.cpu1.num_func_calls                     182742                       # number of times a function call or return occured
+system.cpu1.num_idle_cycles              3734312190.077655                       # Number of idle cycles
 system.cpu1.num_insts                         5931958                       # Number of instructions executed
-system.cpu1.num_refs                          1926244                       # Number of memory references
+system.cpu1.num_int_alu_accesses              5550578                       # Number of integer alu accesses
+system.cpu1.num_int_insts                     5550578                       # number of integer instructions
+system.cpu1.num_int_register_reads            7657288                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           4163275                       # number of times the integer registers were written
+system.cpu1.num_load_insts                    1170888                       # Number of load instructions
+system.cpu1.num_mem_refs                      1926244                       # number of memory refs
+system.cpu1.num_store_insts                    755356                       # Number of store instructions
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index c5b353159..6d9c221c4 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -1,24 +1,33 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -158,7 +167,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -178,7 +187,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -304,7 +313,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -775,7 +784,9 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
+ctrl_offset=0
 disks=system.disk0 system.disk2
+io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
index 83c71fc5c..0372a3b05 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
@@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 85e98e7a4..644d4ca07 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 23:00:12
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 23:09:41
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:46:17
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:46:32
+M5 executing on burrito
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index e2b7c8ed7..3b6776214 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4413707                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 325356                       # Number of bytes of host memory used
-host_seconds                                    13.60                       # Real time elapsed on the host
-host_tick_rate                           134480396261                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1616180                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 311108                       # Number of bytes of host memory used
+host_seconds                                    37.15                       # Real time elapsed on the host
+host_tick_rate                            49243802130                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_seconds                                  1.829332                       # Number of seconds simulated
@@ -297,8 +297,24 @@ system.cpu.kern.syscall::147                        2      0.61%    100.00% # nu
 system.cpu.kern.syscall::total                    326                       # number of syscalls executed
 system.cpu.not_idle_fraction                 0.016415                       # Percentage of non-idle cycles
 system.cpu.numCycles                       3658664408                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles               60055428.819193                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      7110746                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
+system.cpu.num_fp_insts                        324460                       # number of float instructions
+system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
+system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
+system.cpu.num_idle_cycles               3598608979.180807                       # Number of idle cycles
 system.cpu.num_insts                         60038305                       # Number of instructions executed
-system.cpu.num_refs                          16115709                       # Number of memory references
+system.cpu.num_int_alu_accesses              55913521                       # Number of integer alu accesses
+system.cpu.num_int_insts                     55913521                       # number of integer instructions
+system.cpu.num_int_register_reads            76953934                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           41740225                       # number of times the integer registers were written
+system.cpu.num_load_insts                     9747513                       # Number of load instructions
+system.cpu.num_mem_refs                      16115709                       # number of memory refs
+system.cpu.num_store_insts                    6368196                       # Number of store instructions
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index ef977d929..41a7379e1 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -1,24 +1,33 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -259,7 +268,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -279,7 +288,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -405,7 +414,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -876,7 +885,9 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
+ctrl_offset=0
 disks=system.disk0 system.disk2
+io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
index 83c71fc5c..0372a3b05 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
@@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 8585e8d27..8f8e92a25 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 23:00:12
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 23:10:42
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:46:17
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:46:32
+M5 executing on burrito
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 562628000
 Exiting @ tick 1958647095000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 0517b4d72..6e0648c43 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1781653                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 323564                       # Number of bytes of host memory used
-host_seconds                                    33.32                       # Real time elapsed on the host
-host_tick_rate                            58791386546                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 901052                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 309020                       # Number of bytes of host memory used
+host_seconds                                    65.87                       # Real time elapsed on the host
+host_tick_rate                            29733229075                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    59355643                       # Number of instructions simulated
 sim_seconds                                  1.958647                       # Number of seconds simulated
@@ -360,8 +360,24 @@ system.cpu0.kern.syscall::147                       2      0.90%    100.00% # nu
 system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
 system.cpu0.not_idle_fraction                0.060263                       # Percentage of non-idle cycles
 system.cpu0.numCycles                      3916023774                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.num_busy_cycles              235989726.444158                       # Number of busy cycles
+system.cpu0.num_conditional_control_insts      6237040                       # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses                293967                       # Number of float alu accesses
+system.cpu0.num_fp_insts                       293967                       # number of float instructions
+system.cpu0.num_fp_register_reads              143353                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             146452                       # number of times the floating registers were written
+system.cpu0.num_func_calls                    1426863                       # number of times a function call or return occured
+system.cpu0.num_idle_cycles              3680034047.555842                       # Number of idle cycles
 system.cpu0.num_insts                        54072652                       # Number of instructions executed
-system.cpu0.num_refs                         14724357                       # Number of memory references
+system.cpu0.num_int_alu_accesses             50043234                       # Number of integer alu accesses
+system.cpu0.num_int_insts                    50043234                       # number of integer instructions
+system.cpu0.num_int_register_reads           68528072                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          37080372                       # number of times the integer registers were written
+system.cpu0.num_load_insts                    8664914                       # Number of load instructions
+system.cpu0.num_mem_refs                     14724357                       # number of memory refs
+system.cpu0.num_store_insts                   6059443                       # Number of store instructions
 system.cpu1.dcache.LoadLockedReq_accesses::0        12766                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        12766                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271                       # average LoadLockedReq miss latency
@@ -691,8 +707,24 @@ system.cpu1.kern.syscall::132                       3      2.88%    100.00% # nu
 system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
 system.cpu1.not_idle_fraction                0.004865                       # Percentage of non-idle cycles
 system.cpu1.numCycles                      3917294190                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.num_busy_cycles              19057169.001990                       # Number of busy cycles
+system.cpu1.num_conditional_control_insts       510974                       # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses                 34031                       # Number of float alu accesses
+system.cpu1.num_fp_insts                        34031                       # number of float instructions
+system.cpu1.num_fp_register_reads               22062                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              21862                       # number of times the floating registers were written
+system.cpu1.num_func_calls                     158031                       # number of times a function call or return occured
+system.cpu1.num_idle_cycles              3898237020.998010                       # Number of idle cycles
 system.cpu1.num_insts                         5282991                       # Number of instructions executed
-system.cpu1.num_refs                          1710778                       # Number of memory references
+system.cpu1.num_int_alu_accesses              4948310                       # Number of integer alu accesses
+system.cpu1.num_int_insts                     4948310                       # number of integer instructions
+system.cpu1.num_int_register_reads            6886066                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           3732878                       # number of times the integer registers were written
+system.cpu1.num_load_insts                    1056124                       # Number of load instructions
+system.cpu1.num_mem_refs                      1710778                       # number of memory refs
+system.cpu1.num_store_insts                    654654                       # Number of store instructions
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 14aa8c52d..f28d4e037 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -1,24 +1,33 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -155,7 +164,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -175,7 +184,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -301,7 +310,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -772,7 +781,9 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
+ctrl_offset=0
 disks=system.disk0 system.disk2
+io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
index 83c71fc5c..0372a3b05 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
@@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index af718c31f..be2bcef8d 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 23:00:12
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 23:10:12
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:46:17
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:46:32
+M5 executing on burrito
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1915548867000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 37bf681b4..5f1750494 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1917155                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 322176                       # Number of bytes of host memory used
-host_seconds                                    29.28                       # Real time elapsed on the host
-host_tick_rate                            65417896896                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1077887                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 307624                       # Number of bytes of host memory used
+host_seconds                                    52.08                       # Real time elapsed on the host
+host_tick_rate                            36780244064                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    56137087                       # Number of instructions simulated
 sim_seconds                                  1.915549                       # Number of seconds simulated
@@ -341,8 +341,24 @@ system.cpu.kern.syscall::147                        2      0.61%    100.00% # nu
 system.cpu.kern.syscall::total                    326                       # number of syscalls executed
 system.cpu.not_idle_fraction                 0.063469                       # Percentage of non-idle cycles
 system.cpu.numCycles                       3831097734                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles               243154546.001873                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      6464616                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                 324192                       # Number of float alu accesses
+system.cpu.num_fp_insts                        324192                       # number of float instructions
+system.cpu.num_fp_register_reads               163510                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166384                       # number of times the floating registers were written
+system.cpu.num_func_calls                     1482242                       # number of times a function call or return occured
+system.cpu.num_idle_cycles               3587943187.998127                       # Number of idle cycles
 system.cpu.num_insts                         56137087                       # Number of instructions executed
-system.cpu.num_refs                          15462519                       # Number of memory references
+system.cpu.num_int_alu_accesses              52011214                       # Number of integer alu accesses
+system.cpu.num_int_insts                     52011214                       # number of integer instructions
+system.cpu.num_int_register_reads            71259077                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38485860                       # number of times the integer registers were written
+system.cpu.num_load_insts                     9094324                       # Number of load instructions
+system.cpu.num_mem_refs                      15462519                       # number of memory refs
+system.cpu.num_store_insts                    6368195                       # Number of store instructions
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 505488008..79021a958 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
@@ -9,13 +11,20 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
 boot_cpu_frequency=500
 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+kernel=/dist/m5/system/binaries/vmlinux.arm
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -158,7 +167,7 @@ type=ExeTracer
 
 [system.diskmem]
 type=PhysicalMemory
-file=/chips/pd/randd/dist/disks/ael-arm.ext2
+file=/dist/m5/system/disks/ael-arm.ext2
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 05fcdedb2..ba4c6742c 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 15 2010 11:17:32
-M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip
-M5 started Oct 15 2010 11:17:48
-M5 executing on aus-bc3-b4
-command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
+M5 compiled Feb  7 2011 01:53:13
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:53:26
+M5 executing on burrito
+command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 25821310500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 1bfa8bc8a..0a7542a7c 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1831927                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 384484                       # Number of bytes of host memory used
-host_seconds                                    27.81                       # Real time elapsed on the host
-host_tick_rate                              928414614                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 739167                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 360776                       # Number of bytes of host memory used
+host_seconds                                    68.93                       # Real time elapsed on the host
+host_tick_rate                              374609475                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    50949504                       # Number of instructions simulated
 sim_seconds                                  0.025821                       # Number of seconds simulated
@@ -225,8 +225,24 @@ system.cpu.kern.inst.arm                            0                       # nu
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                         51642622                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                   51642622                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                   6059                       # Number of float alu accesses
+system.cpu.num_fp_insts                          6059                       # number of float instructions
+system.cpu.num_fp_register_reads                 4227                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                1834                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         50949504                       # Number of instructions executed
-system.cpu.num_refs                          16092645                       # Number of memory references
+system.cpu.num_int_alu_accesses              41395090                       # Number of integer alu accesses
+system.cpu.num_int_insts                     41395090                       # number of integer instructions
+system.cpu.num_int_register_reads           128438705                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           33973128                       # number of times the integer registers were written
+system.cpu.num_load_insts                     9082722                       # Number of load instructions
+system.cpu.num_mem_refs                      16092645                       # number of memory refs
+system.cpu.num_store_insts                    7009923                       # Number of store instructions
 system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
index 586cb6b73..53b01d583 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
@@ -1 +1 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
+build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index c7f419728..4fad32362 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
@@ -16,6 +18,13 @@ mem_mode=timing
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.bridge]
 type=Bridge
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 8382cb48d..994dfb6a2 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 18:36:49
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 18:36:52
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:53:13
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:53:26
+M5 executing on burrito
 command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 157177a6b..85fb99220 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1461109                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 340352                       # Number of bytes of host memory used
-host_seconds                                    34.61                       # Real time elapsed on the host
-host_tick_rate                             3314430509                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 433208                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 360908                       # Number of bytes of host memory used
+host_seconds                                   116.74                       # Real time elapsed on the host
+host_tick_rate                              982709659                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    50572425                       # Number of instructions simulated
 sim_seconds                                  0.114721                       # Number of seconds simulated
@@ -273,8 +273,24 @@ system.cpu.kern.inst.arm                            0                       # nu
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        229442148                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  229442148                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                   6058                       # Number of float alu accesses
+system.cpu.num_fp_insts                          6058                       # number of float instructions
+system.cpu.num_fp_register_reads                 4226                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                1834                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         50572425                       # Number of instructions executed
-system.cpu.num_refs                          16289993                       # Number of memory references
+system.cpu.num_int_alu_accesses              41827211                       # Number of integer alu accesses
+system.cpu.num_int_insts                     41827211                       # number of integer instructions
+system.cpu.num_int_register_reads           137988684                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           34313952                       # number of times the integer registers were written
+system.cpu.num_load_insts                     9208240                       # Number of load instructions
+system.cpu.num_mem_refs                      16289993                       # number of memory refs
+system.cpu.num_store_insts                    7081753                       # Number of store instructions
 system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
index 19639b6dab32b8cf779b5785ddc49d26dc98bb71..f3053783c0fa0ac0997a69cbfbe59701fecfdfec 100644
GIT binary patch
delta 38
ucmaDN_e5^PYaT8`Qwu#yOLHSr<H=unthfwK%=HW`3`~rSH(T;*GXVhe{|deU

delta 38
ucmaDN_e5^PYaT8IOJhAt3o{c_)5%|Xthf|RE%i(d3=Ay{He2#)GXVhcAPSuT

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 8b31e35e7..1a56ca25e 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
index d7e9fb267..5ef0286ce 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  9 2010 10:38:04
-M5 revision f4362ffd810f+ 7737+ default tip
-M5 started Nov  9 2010 22:11:58
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:49
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index 4b1bec9b7..e65e62021 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2960881                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 193980                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
-host_tick_rate                             1478428114                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1417565                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214360                       # Number of bytes of host memory used
+host_seconds                                     0.35                       # Real time elapsed on the host
+host_tick_rate                              708232428                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           500032                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                     500032                       # Number of busy cycles
+system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
+system.cpu.num_fp_insts                            32                       # number of float instructions
+system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
+system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                           500001                       # Number of instructions executed
-system.cpu.num_refs                            180793                       # Number of memory references
+system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
+system.cpu.num_int_insts                       474689                       # number of integer instructions
+system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
+system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
+system.cpu.num_load_insts                      124443                       # Number of load instructions
+system.cpu.num_mem_refs                        180793                       # number of memory refs
+system.cpu.num_store_insts                      56350                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 380aa38da..466dd444b 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
index 35ea05083..2fab9f5ba 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  9 2010 10:38:04
-M5 revision f4362ffd810f+ 7737+ default tip
-M5 started Nov  9 2010 22:11:58
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:48
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index 8d21cdbb4..3dc7b5670 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1193890                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201748                       # Number of bytes of host memory used
-host_seconds                                     0.42                       # Real time elapsed on the host
-host_tick_rate                             1737027103                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 663064                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 222076                       # Number of bytes of host memory used
+host_seconds                                     0.75                       # Real time elapsed on the host
+host_tick_rate                              964960959                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000728                       # Number of seconds simulated
@@ -226,8 +226,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                          1455858                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                    1455858                       # Number of busy cycles
+system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
+system.cpu.num_fp_insts                            32                       # number of float instructions
+system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
+system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                           500001                       # Number of instructions executed
-system.cpu.num_refs                            180793                       # Number of memory references
+system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
+system.cpu.num_int_insts                       474689                       # number of integer instructions
+system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
+system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
+system.cpu.num_load_insts                      124443                       # Number of load instructions
+system.cpu.num_mem_refs                        180793                       # number of memory refs
+system.cpu.num_store_insts                      56350                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index f95ff0355..9f134009a 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu0]
 type=AtomicSimpleCPU
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 21b8e7313..174fa89ad 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  9 2010 10:38:04
-M5 revision f4362ffd810f+ 7737+ default tip
-M5 started Nov  9 2010 22:11:58
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:48
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 81431004c..9f848a332 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2770469                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1126824                       # Number of bytes of host memory used
-host_seconds                                     0.72                       # Real time elapsed on the host
-host_tick_rate                              346193150                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1366260                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1147168                       # Number of bytes of host memory used
+host_seconds                                     1.46                       # Real time elapsed on the host
+host_tick_rate                              170760827                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     2000004                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
@@ -145,8 +145,24 @@ system.cpu0.itb.write_hits                          0                       # DT
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu0.num_fp_insts                           32                       # number of float instructions
+system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu0.num_insts                          500001                       # Number of instructions executed
-system.cpu0.num_refs                           180793                       # Number of memory references
+system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu0.num_int_insts                      474689                       # number of integer instructions
+system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu0.num_load_insts                     124443                       # Number of load instructions
+system.cpu0.num_mem_refs                       180793                       # number of memory refs
+system.cpu0.num_store_insts                     56350                       # Number of store instructions
 system.cpu0.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_hits                124111                       # number of ReadReq hits
@@ -285,8 +301,24 @@ system.cpu1.itb.write_hits                          0                       # DT
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu1.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu1.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu1.num_fp_insts                           32                       # number of float instructions
+system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu1.num_insts                          500001                       # Number of instructions executed
-system.cpu1.num_refs                           180793                       # Number of memory references
+system.cpu1.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu1.num_int_insts                      474689                       # number of integer instructions
+system.cpu1.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu1.num_load_insts                     124443                       # Number of load instructions
+system.cpu1.num_mem_refs                       180793                       # number of memory refs
+system.cpu1.num_store_insts                     56350                       # Number of store instructions
 system.cpu1.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu2.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_hits                124111                       # number of ReadReq hits
@@ -425,8 +457,24 @@ system.cpu2.itb.write_hits                          0                       # DT
 system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu2.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu2.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu2.num_fp_insts                           32                       # number of float instructions
+system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu2.num_insts                          500001                       # Number of instructions executed
-system.cpu2.num_refs                           180793                       # Number of memory references
+system.cpu2.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu2.num_int_insts                      474689                       # number of integer instructions
+system.cpu2.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu2.num_load_insts                     124443                       # Number of load instructions
+system.cpu2.num_mem_refs                       180793                       # number of memory refs
+system.cpu2.num_store_insts                     56350                       # Number of store instructions
 system.cpu2.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu3.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_hits                124111                       # number of ReadReq hits
@@ -565,8 +613,24 @@ system.cpu3.itb.write_hits                          0                       # DT
 system.cpu3.itb.write_misses                        0                       # DTB write misses
 system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu3.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu3.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu3.num_fp_insts                           32                       # number of float instructions
+system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu3.num_insts                          500001                       # Number of instructions executed
-system.cpu3.num_refs                           180793                       # Number of memory references
+system.cpu3.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu3.num_int_insts                      474689                       # number of integer instructions
+system.cpu3.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu3.num_load_insts                     124443                       # Number of load instructions
+system.cpu3.num_mem_refs                       180793                       # number of memory refs
+system.cpu3.num_store_insts                     56350                       # Number of store instructions
 system.cpu3.workload.PROG:num_syscalls             18                       # Number of system calls
 system.l2c.ReadExReq_accesses::0                  139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                  139                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index a23113a37..9ec264236 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu0]
 type=TimingSimpleCPU
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 98d9eda34..fa3024167 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -8,8 +8,8 @@ hack: be nice to actually delete the event here
 
 gzip: stdout: Broken pipe
 
+gzip: 
 gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+stdout: Broken pipe
 
 gzip: stdout: Broken pipe
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index 09966aa49..af5204214 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  9 2010 10:38:04
-M5 revision f4362ffd810f+ 7737+ default tip
-M5 started Nov  9 2010 22:11:58
-M5 executing on zizzer
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index dbaf84851..9dfa01a0d 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1961801                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 209312                       # Number of bytes of host memory used
-host_seconds                                     1.02                       # Real time elapsed on the host
-host_tick_rate                              714851017                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 730494                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 229664                       # Number of bytes of host memory used
+host_seconds                                     2.74                       # Real time elapsed on the host
+host_tick_rate                              266213751                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     1999954                       # Number of instructions simulated
 sim_seconds                                  0.000729                       # Number of seconds simulated
@@ -163,8 +163,24 @@ system.cpu0.itb.write_hits                          0                       # DT
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                         1457840                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.num_busy_cycles                   1457840                       # Number of busy cycles
+system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu0.num_fp_insts                           32                       # number of float instructions
+system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu0.num_insts                          500001                       # Number of instructions executed
-system.cpu0.num_refs                           180793                       # Number of memory references
+system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu0.num_int_insts                      474689                       # number of integer instructions
+system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu0.num_load_insts                     124443                       # Number of load instructions
+system.cpu0.num_mem_refs                       180793                       # number of memory refs
+system.cpu0.num_store_insts                     56350                       # Number of store instructions
 system.cpu0.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309                       # average ReadReq miss latency
@@ -321,8 +337,24 @@ system.cpu1.itb.write_hits                          0                       # DT
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu1.numCycles                         1457840                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.num_busy_cycles                   1457840                       # Number of busy cycles
+system.cpu1.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu1.num_fp_insts                           32                       # number of float instructions
+system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu1.num_insts                          499993                       # Number of instructions executed
-system.cpu1.num_refs                           180792                       # Number of memory references
+system.cpu1.num_int_alu_accesses               474681                       # Number of integer alu accesses
+system.cpu1.num_int_insts                      474681                       # number of integer instructions
+system.cpu1.num_int_register_reads             654273                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            371536                       # number of times the integer registers were written
+system.cpu1.num_load_insts                     124443                       # Number of load instructions
+system.cpu1.num_mem_refs                       180792                       # number of memory refs
+system.cpu1.num_store_insts                     56349                       # Number of store instructions
 system.cpu1.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu2.dcache.ReadReq_accesses            124433                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086                       # average ReadReq miss latency
@@ -479,8 +511,24 @@ system.cpu2.itb.write_hits                          0                       # DT
 system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu2.numCycles                         1457840                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.num_busy_cycles                   1457840                       # Number of busy cycles
+system.cpu2.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
+system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu2.num_fp_insts                           32                       # number of float instructions
+system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu2.num_insts                          499982                       # Number of instructions executed
-system.cpu2.num_refs                           180789                       # Number of memory references
+system.cpu2.num_int_alu_accesses               474671                       # Number of integer alu accesses
+system.cpu2.num_int_insts                      474671                       # number of integer instructions
+system.cpu2.num_int_register_reads             654261                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            371526                       # number of times the integer registers were written
+system.cpu2.num_load_insts                     124440                       # Number of load instructions
+system.cpu2.num_mem_refs                       180789                       # number of memory refs
+system.cpu2.num_store_insts                     56349                       # Number of store instructions
 system.cpu2.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu3.dcache.ReadReq_accesses            124431                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827                       # average ReadReq miss latency
@@ -637,8 +685,24 @@ system.cpu3.itb.write_hits                          0                       # DT
 system.cpu3.itb.write_misses                        0                       # DTB write misses
 system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu3.numCycles                         1457840                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.num_busy_cycles                   1457840                       # Number of busy cycles
+system.cpu3.num_conditional_control_insts        38178                       # number of instructions that are conditional controls
+system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu3.num_fp_insts                           32                       # number of float instructions
+system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu3.num_insts                          499978                       # Number of instructions executed
-system.cpu3.num_refs                           180787                       # Number of memory references
+system.cpu3.num_int_alu_accesses               474667                       # Number of integer alu accesses
+system.cpu3.num_int_insts                      474667                       # number of integer instructions
+system.cpu3.num_int_register_reads             654256                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            371523                       # number of times the integer registers were written
+system.cpu3.num_load_insts                     124438                       # Number of load instructions
+system.cpu3.num_mem_refs                       180787                       # number of memory refs
+system.cpu3.num_store_insts                     56349                       # Number of store instructions
 system.cpu3.workload.PROG:num_syscalls             18                       # Number of system calls
 system.l2c.ReadExReq_accesses::0                  139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                  139                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 17847f641..08b40bb1a 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu0]
 type=DerivO3CPU
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index ac49cfc17..d3d241630 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 21:17:52
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 21:19:18
-M5 executing on zizzer
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:39
+M5 executing on burrito
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 1034fcecd..acba85fd7 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 133732                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214280                       # Number of bytes of host memory used
-host_seconds                                     8.62                       # Real time elapsed on the host
-host_tick_rate                               13623692                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  67069                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 234672                       # Number of bytes of host memory used
+host_seconds                                    17.20                       # Real time elapsed on the host
+host_tick_rate                                6832636                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     1153323                       # Number of instructions simulated
 sim_seconds                                  0.000117                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu0.commit.COM:committed_per_cycle::min_value            0
 system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::total       214839                       # Number of insts commited each cycle
 system.cpu0.commit.COM:count                   534547                       # Number of instructions committed
+system.cpu0.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
+system.cpu0.commit.COM:function_calls               0                       # Number of function calls committed.
+system.cpu0.commit.COM:int_insts               359798                       # Number of committed integer instructions.
 system.cpu0.commit.COM:loads                   174318                       # Number of loads committed
 system.cpu0.commit.COM:membars                     84                       # Number of memory barriers committed
 system.cpu0.commit.COM:refs                    261983                       # Number of memory references committed
@@ -162,6 +165,7 @@ system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::total              216884                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
 system.cpu0.icache.ReadReq_accesses              5264                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_avg_miss_latency 39056.216931                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37012.315271                       # average ReadReq mshr miss latency
@@ -261,6 +265,8 @@ system.cpu0.iew.lsq.thread.0.squashedStores         1081                       #
 system.cpu0.iew.memOrderViolationEvents            74                       # Number of memory order violations
 system.cpu0.iew.predictedNotTakenIncorrect          821                       # Number of branches that were predicted not taken incorrectly
 system.cpu0.iew.predictedTakenIncorrect           425                       # Number of branches that were predicted taken incorrectly
+system.cpu0.int_regfile_reads                  812944                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 365773                       # number of integer regfile writes
 system.cpu0.ipc                              1.907193                       # IPC: Instructions Per Cycle
 system.cpu0.ipc_total                        1.907193                       # IPC: Total IPC of All Threads
 system.cpu0.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -352,6 +358,14 @@ system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::total       216884                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:rate                    1.936032                       # Inst issue rate
+system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
+system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu0.iq.int_alu_accesses                455183                       # Number of integer alu accesses
+system.cpu0.iq.int_inst_queue_reads           1127113                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_wakeup_accesses       453412                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.int_inst_queue_writes           465644                       # Number of integer instruction queue writes
 system.cpu0.iq.iqInstsAdded                    456518                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu0.iq.iqInstsIssued                   454956                       # Number of instructions issued
 system.cpu0.iq.iqNonSpecInstsAdded                825                       # Number of non-speculative instructions added to the IQ
@@ -363,7 +377,11 @@ system.cpu0.memDep0.conflictingLoads            86252                       # Nu
 system.cpu0.memDep0.conflictingStores           86102                       # Number of conflicting stores.
 system.cpu0.memDep0.insertedLoads              176000                       # Number of loads inserted to the mem dependence unit.
 system.cpu0.memDep0.insertedStores              88746                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.misc_regfile_reads                 265411                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
 system.cpu0.numCycles                          234994                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.rename.RENAME:BlockCycles            1211                       # Number of cycles rename is blocking
 system.cpu0.rename.RENAME:CommittedMaps        361468                       # Number of HB maps that are committed
 system.cpu0.rename.RENAME:IQFullEvents              6                       # Number of times rename has blocked due to IQ full
@@ -376,10 +394,13 @@ system.cpu0.rename.RENAME:RunCycles            180641                       # Nu
 system.cpu0.rename.RENAME:SquashCycles           2062                       # Number of cycles rename is squashing
 system.cpu0.rename.RENAME:UnblockCycles           697                       # Number of cycles rename is unblocking
 system.cpu0.rename.RENAME:UndoneMaps            10322                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:int_rename_lookups      1089130                       # Number of integer rename lookups
 system.cpu0.rename.RENAME:serializeStallCycles        11540                       # count of cycles rename stalled for serializing inst
 system.cpu0.rename.RENAME:serializingInsts          809                       # count of serializing insts renamed
 system.cpu0.rename.RENAME:skidInsts              4202                       # count of insts added to the skid buffer
 system.cpu0.rename.RENAME:tempSerializingInsts          812                       # count of temporary serializing insts renamed
+system.cpu0.rob.rob_reads                      757548                       # The number of ROB reads
+system.cpu0.rob.rob_writes                    1090250                       # The number of ROB writes
 system.cpu0.timesIdled                            337                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
@@ -411,6 +432,9 @@ system.cpu1.commit.COM:committed_per_cycle::min_value            0
 system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::total       187667                       # Number of insts commited each cycle
 system.cpu1.commit.COM:count                   221435                       # Number of instructions committed
+system.cpu1.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
+system.cpu1.commit.COM:function_calls               0                       # Number of function calls committed.
+system.cpu1.commit.COM:int_insts               150322                       # Number of committed integer instructions.
 system.cpu1.commit.COM:loads                    60856                       # Number of loads committed
 system.cpu1.commit.COM:membars                   9088                       # Number of memory barriers committed
 system.cpu1.commit.COM:refs                     87006                       # Number of memory references committed
@@ -536,6 +560,7 @@ system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::total              196087                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
 system.cpu1.icache.ReadReq_accesses             27242                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_avg_miss_latency 15144.329897                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12327.702703                       # average ReadReq mshr miss latency
@@ -635,6 +660,8 @@ system.cpu1.iew.lsq.thread.0.squashedStores          732                       #
 system.cpu1.iew.memOrderViolationEvents            35                       # Number of memory order violations
 system.cpu1.iew.predictedNotTakenIncorrect          189                       # Number of branches that were predicted not taken incorrectly
 system.cpu1.iew.predictedTakenIncorrect          1010                       # Number of branches that were predicted taken incorrectly
+system.cpu1.int_regfile_reads                  321648                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 150288                       # number of integer regfile writes
 system.cpu1.ipc                              0.902137                       # IPC: Instructions Per Cycle
 system.cpu1.ipc_total                        0.902137                       # IPC: Total IPC of All Threads
 system.cpu1.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -726,6 +753,14 @@ system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::total       196087                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:rate                    0.970635                       # Inst issue rate
+system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
+system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu1.iq.int_alu_accesses                194246                       # Number of integer alu accesses
+system.cpu1.iq.int_inst_queue_reads            584396                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_wakeup_accesses       192754                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.int_inst_queue_writes           203505                       # Number of integer instruction queue writes
 system.cpu1.iq.iqInstsAdded                    186439                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu1.iq.iqInstsIssued                   194061                       # Number of instructions issued
 system.cpu1.iq.iqNonSpecInstsAdded              10484                       # Number of non-speculative instructions added to the IQ
@@ -737,7 +772,11 @@ system.cpu1.memDep0.conflictingLoads            31889                       # Nu
 system.cpu1.memDep0.conflictingStores           22377                       # Number of conflicting stores.
 system.cpu1.memDep0.insertedLoads               62331                       # Number of loads inserted to the mem dependence unit.
 system.cpu1.memDep0.insertedStores              26882                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.misc_regfile_reads                  89554                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu1.numCycles                          199932                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.rename.RENAME:BlockCycles            9891                       # Number of cycles rename is blocking
 system.cpu1.rename.RENAME:CommittedMaps        147748                       # Number of HB maps that are committed
 system.cpu1.rename.RENAME:IQFullEvents             48                       # Number of times rename has blocked due to IQ full
@@ -750,10 +789,13 @@ system.cpu1.rename.RENAME:RunCycles             92302                       # Nu
 system.cpu1.rename.RENAME:SquashCycles           1784                       # Number of cycles rename is squashing
 system.cpu1.rename.RENAME:UnblockCycles           562                       # Number of cycles rename is unblocking
 system.cpu1.rename.RENAME:UndoneMaps             8137                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:int_rename_lookups       422855                       # Number of integer rename lookups
 system.cpu1.rename.RENAME:serializeStallCycles        13360                       # count of cycles rename stalled for serializing inst
 system.cpu1.rename.RENAME:serializingInsts          970                       # count of serializing insts renamed
 system.cpu1.rename.RENAME:skidInsts              2743                       # count of insts added to the skid buffer
 system.cpu1.rename.RENAME:tempSerializingInsts         1022                       # count of temporary serializing insts renamed
+system.cpu1.rob.rob_reads                      416274                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     461144                       # The number of ROB writes
 system.cpu1.timesIdled                            297                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu2.BPredUnit.BTBHits                   58194                       # Number of BTB hits
@@ -784,6 +826,9 @@ system.cpu2.commit.COM:committed_per_cycle::min_value            0
 system.cpu2.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu2.commit.COM:committed_per_cycle::total       185916                       # Number of insts commited each cycle
 system.cpu2.commit.COM:count                   330777                       # Number of instructions committed
+system.cpu2.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
+system.cpu2.commit.COM:function_calls               0                       # Number of function calls committed.
+system.cpu2.commit.COM:int_insts               226484                       # Number of committed integer instructions.
 system.cpu2.commit.COM:loads                    98945                       # Number of loads committed
 system.cpu2.commit.COM:membars                   4183                       # Number of memory barriers committed
 system.cpu2.commit.COM:refs                    146579                       # Number of memory references committed
@@ -909,6 +954,7 @@ system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::total              194280                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
 system.cpu2.icache.ReadReq_accesses             17027                       # number of ReadReq accesses(hits+misses)
 system.cpu2.icache.ReadReq_avg_miss_latency 21608.921162                       # average ReadReq miss latency
 system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18272.935780                       # average ReadReq mshr miss latency
@@ -1008,6 +1054,8 @@ system.cpu2.iew.lsq.thread.0.squashedStores          766                       #
 system.cpu2.iew.memOrderViolationEvents            35                       # Number of memory order violations
 system.cpu2.iew.predictedNotTakenIncorrect          199                       # Number of branches that were predicted not taken incorrectly
 system.cpu2.iew.predictedTakenIncorrect           991                       # Number of branches that were predicted taken incorrectly
+system.cpu2.int_regfile_reads                  500577                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 231428                       # number of integer regfile writes
 system.cpu2.ipc                              1.392607                       # IPC: Instructions Per Cycle
 system.cpu2.ipc_total                        1.392607                       # IPC: Total IPC of All Threads
 system.cpu2.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -1099,6 +1147,14 @@ system.cpu2.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu2.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu2.iq.ISSUE:issued_per_cycle::total       194280                       # Number of insts issued each cycle
 system.cpu2.iq.ISSUE:rate                    1.437167                       # Inst issue rate
+system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
+system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu2.iq.int_alu_accesses                287114                       # Number of integer alu accesses
+system.cpu2.iq.int_inst_queue_reads            768311                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_wakeup_accesses       285574                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.int_inst_queue_writes           296099                       # Number of integer instruction queue writes
 system.cpu2.iq.iqInstsAdded                    284164                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu2.iq.iqInstsIssued                   286916                       # Number of instructions issued
 system.cpu2.iq.iqNonSpecInstsAdded               5428                       # Number of non-speculative instructions added to the IQ
@@ -1110,7 +1166,11 @@ system.cpu2.memDep0.conflictingLoads            48437                       # Nu
 system.cpu2.memDep0.conflictingStores           43927                       # Number of conflicting stores.
 system.cpu2.memDep0.insertedLoads              100435                       # Number of loads inserted to the mem dependence unit.
 system.cpu2.memDep0.insertedStores              48400                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.misc_regfile_reads                 149234                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu2.numCycles                          199640                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.rename.RENAME:BlockCycles            5634                       # Number of cycles rename is blocking
 system.cpu2.rename.RENAME:CommittedMaps        228819                       # Number of HB maps that are committed
 system.cpu2.rename.RENAME:IQFullEvents             67                       # Number of times rename has blocked due to IQ full
@@ -1123,10 +1183,13 @@ system.cpu2.rename.RENAME:RunCycles            120203                       # Nu
 system.cpu2.rename.RENAME:SquashCycles           1740                       # Number of cycles rename is squashing
 system.cpu2.rename.RENAME:UnblockCycles           620                       # Number of cycles rename is unblocking
 system.cpu2.rename.RENAME:UndoneMaps             8187                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.RENAME:int_rename_lookups       661216                       # Number of integer rename lookups
 system.cpu2.rename.RENAME:serializeStallCycles        12791                       # count of cycles rename stalled for serializing inst
 system.cpu2.rename.RENAME:serializingInsts          940                       # count of serializing insts renamed
 system.cpu2.rename.RENAME:skidInsts              2775                       # count of insts added to the skid buffer
 system.cpu2.rename.RENAME:tempSerializingInsts          995                       # count of temporary serializing insts renamed
+system.cpu2.rob.rob_reads                      523697                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     679481                       # The number of ROB writes
 system.cpu2.timesIdled                            296                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu3.BPredUnit.BTBHits                   53101                       # Number of BTB hits
@@ -1157,6 +1220,9 @@ system.cpu3.commit.COM:committed_per_cycle::min_value            0
 system.cpu3.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu3.commit.COM:committed_per_cycle::total       187872                       # Number of insts commited each cycle
 system.cpu3.commit.COM:count                   296008                       # Number of instructions committed
+system.cpu3.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
+system.cpu3.commit.COM:function_calls               0                       # Number of function calls committed.
+system.cpu3.commit.COM:int_insts               202157                       # Number of committed integer instructions.
 system.cpu3.commit.COM:loads                    86777                       # Number of loads committed
 system.cpu3.commit.COM:membars                   5899                       # Number of memory barriers committed
 system.cpu3.commit.COM:refs                    127476                       # Number of memory references committed
@@ -1282,6 +1348,7 @@ system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::total              196296                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
 system.cpu3.icache.ReadReq_accesses             20572                       # number of ReadReq accesses(hits+misses)
 system.cpu3.icache.ReadReq_avg_miss_latency 14541.928721                       # average ReadReq miss latency
 system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11822.799097                       # average ReadReq mshr miss latency
@@ -1381,6 +1448,8 @@ system.cpu3.iew.lsq.thread.0.squashedStores          782                       #
 system.cpu3.iew.memOrderViolationEvents            34                       # Number of memory order violations
 system.cpu3.iew.predictedNotTakenIncorrect          194                       # Number of branches that were predicted not taken incorrectly
 system.cpu3.iew.predictedTakenIncorrect          1002                       # Number of branches that were predicted taken incorrectly
+system.cpu3.int_regfile_reads                  443221                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 205359                       # number of integer regfile writes
 system.cpu3.ipc                              1.237689                       # IPC: Instructions Per Cycle
 system.cpu3.ipc_total                        1.237689                       # IPC: Total IPC of All Threads
 system.cpu3.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -1472,6 +1541,14 @@ system.cpu3.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu3.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu3.iq.ISSUE:issued_per_cycle::total       196296                       # Number of insts issued each cycle
 system.cpu3.iq.ISSUE:rate                    1.290801                       # Inst issue rate
+system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
+system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu3.iq.int_alu_accesses                257546                       # Number of integer alu accesses
+system.cpu3.iq.int_inst_queue_reads            711191                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_wakeup_accesses       256019                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.int_inst_queue_writes           266954                       # Number of integer instruction queue writes
 system.cpu3.iq.iqInstsAdded                    253019                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu3.iq.iqInstsIssued                   257347                       # Number of instructions issued
 system.cpu3.iq.iqNonSpecInstsAdded               7241                       # Number of non-speculative instructions added to the IQ
@@ -1483,7 +1560,11 @@ system.cpu3.memDep0.conflictingLoads            43278                       # Nu
 system.cpu3.memDep0.conflictingStores           36990                       # Number of conflicting stores.
 system.cpu3.memDep0.insertedLoads               88323                       # Number of loads inserted to the mem dependence unit.
 system.cpu3.memDep0.insertedStores              41481                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.misc_regfile_reads                 130106                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu3.numCycles                          199370                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.rename.RENAME:BlockCycles            7226                       # Number of cycles rename is blocking
 system.cpu3.rename.RENAME:CommittedMaps        202775                       # Number of HB maps that are committed
 system.cpu3.rename.RENAME:IQFullEvents             58                       # Number of times rename has blocked due to IQ full
@@ -1496,10 +1577,13 @@ system.cpu3.rename.RENAME:RunCycles            111693                       # Nu
 system.cpu3.rename.RENAME:SquashCycles           1792                       # Number of cycles rename is squashing
 system.cpu3.rename.RENAME:UnblockCycles           593                       # Number of cycles rename is unblocking
 system.cpu3.rename.RENAME:UndoneMaps             8286                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.RENAME:int_rename_lookups       585183                       # Number of integer rename lookups
 system.cpu3.rename.RENAME:serializeStallCycles        13124                       # count of cycles rename stalled for serializing inst
 system.cpu3.rename.RENAME:serializingInsts          957                       # count of serializing insts renamed
 system.cpu3.rename.RENAME:skidInsts              2808                       # count of insts added to the skid buffer
 system.cpu3.rename.RENAME:tempSerializingInsts         1009                       # count of temporary serializing insts renamed
+system.cpu3.rob.rob_reads                      491204                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     610604                       # The number of ROB writes
 system.cpu3.timesIdled                            290                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.l2c.ReadExReq_accesses::0                   94                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                   12                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index e833b46ac..01c43d58b 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu0]
 type=AtomicSimpleCPU
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 9ac3c5e14..2f8db50d8 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:04:32
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:13:36
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 0544aca9b..2fa9a2da1 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1027581                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1133204                       # Number of bytes of host memory used
-host_seconds                                     0.66                       # Real time elapsed on the host
-host_tick_rate                              133016942                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 813548                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1149396                       # Number of bytes of host memory used
+host_seconds                                     0.83                       # Real time elapsed on the host
+host_tick_rate                              105315075                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      677340                       # Number of instructions simulated
 sim_seconds                                  0.000088                       # Number of seconds simulated
@@ -117,8 +117,24 @@ system.cpu0.icache.writebacks                       0                       # nu
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                          175428                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.num_busy_cycles                    175428                       # Number of busy cycles
+system.cpu0.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu0.num_fp_insts                            0                       # number of float instructions
+system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu0.num_insts                          175339                       # Number of instructions executed
-system.cpu0.num_refs                            82398                       # Number of memory references
+system.cpu0.num_int_alu_accesses               120388                       # Number of integer alu accesses
+system.cpu0.num_int_insts                      120388                       # number of integer instructions
+system.cpu0.num_int_register_reads             349308                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            121996                       # number of times the integer registers were written
+system.cpu0.num_load_insts                      54592                       # Number of load instructions
+system.cpu0.num_mem_refs                        82398                       # number of memory refs
+system.cpu0.num_store_insts                     27806                       # Number of store instructions
 system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses             40644                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_hits                 40468                       # number of ReadReq hits
@@ -229,8 +245,24 @@ system.cpu1.icache.writebacks                       0                       # nu
 system.cpu1.idle_fraction                    0.045506                       # Percentage of idle cycles
 system.cpu1.not_idle_fraction                0.954494                       # Percentage of non-idle cycles
 system.cpu1.numCycles                          173308                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.num_busy_cycles              165421.425557                       # Number of busy cycles
+system.cpu1.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu1.num_fp_insts                            0                       # number of float instructions
+system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu1.num_idle_cycles               7886.574443                       # Number of idle cycles
 system.cpu1.num_insts                          167398                       # Number of instructions executed
-system.cpu1.num_refs                            53394                       # Number of memory references
+system.cpu1.num_int_alu_accesses               109926                       # Number of integer alu accesses
+system.cpu1.num_int_insts                      109926                       # number of integer instructions
+system.cpu1.num_int_register_reads             270038                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            100721                       # number of times the integer registers were written
+system.cpu1.num_load_insts                      40652                       # Number of load instructions
+system.cpu1.num_mem_refs                        53394                       # number of memory refs
+system.cpu1.num_store_insts                     12742                       # Number of store instructions
 system.cpu2.dcache.ReadReq_accesses             42354                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_hits                 42192                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_miss_rate         0.003825                       # miss rate for ReadReq accesses
@@ -340,8 +372,24 @@ system.cpu2.icache.writebacks                       0                       # nu
 system.cpu2.idle_fraction                    0.045871                       # Percentage of idle cycles
 system.cpu2.not_idle_fraction                0.954129                       # Percentage of non-idle cycles
 system.cpu2.numCycles                          173308                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.num_busy_cycles              165358.198620                       # Number of busy cycles
+system.cpu2.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu2.num_fp_insts                            0                       # number of float instructions
+system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu2.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu2.num_idle_cycles               7949.801380                       # Number of idle cycles
 system.cpu2.num_insts                          167334                       # Number of instructions executed
-system.cpu2.num_refs                            58537                       # Number of memory references
+system.cpu2.num_int_alu_accesses               113333                       # Number of integer alu accesses
+system.cpu2.num_int_insts                      113333                       # number of integer instructions
+system.cpu2.num_int_register_reads             290613                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            109308                       # number of times the integer registers were written
+system.cpu2.num_load_insts                      42362                       # Number of load instructions
+system.cpu2.num_mem_refs                        58537                       # number of memory refs
+system.cpu2.num_store_insts                     16175                       # Number of store instructions
 system.cpu3.dcache.ReadReq_accesses             41458                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_hits                 41299                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_miss_rate         0.003835                       # miss rate for ReadReq accesses
@@ -451,8 +499,24 @@ system.cpu3.icache.writebacks                       0                       # nu
 system.cpu3.idle_fraction                    0.046241                       # Percentage of idle cycles
 system.cpu3.not_idle_fraction                0.953759                       # Percentage of non-idle cycles
 system.cpu3.numCycles                          173307                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.num_busy_cycles              165293.030003                       # Number of busy cycles
+system.cpu3.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu3.num_fp_insts                            0                       # number of float instructions
+system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu3.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu3.num_idle_cycles               8013.969997                       # Number of idle cycles
 system.cpu3.num_insts                          167269                       # Number of instructions executed
-system.cpu3.num_refs                            55900                       # Number of memory references
+system.cpu3.num_int_alu_accesses               111554                       # Number of integer alu accesses
+system.cpu3.num_int_insts                      111554                       # number of integer instructions
+system.cpu3.num_int_register_reads             280060                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            104916                       # number of times the integer registers were written
+system.cpu3.num_load_insts                      41466                       # Number of load instructions
+system.cpu3.num_mem_refs                        55900                       # number of memory refs
+system.cpu3.num_store_insts                     14434                       # Number of store instructions
 system.l2c.ReadExReq_accesses::0                   99                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                   13                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::2                   12                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 276044213..8968b20fc 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu0]
 type=TimingSimpleCPU
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index cae225db3..14a3c411f 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:03:45
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+M5 compiled Feb  7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 02:16:15
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index a2bed5a68..dff846f53 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 583465                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215700                       # Number of bytes of host memory used
-host_seconds                                     1.12                       # Real time elapsed on the host
-host_tick_rate                              235218525                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 414570                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 231892                       # Number of bytes of host memory used
+host_seconds                                     1.57                       # Real time elapsed on the host
+host_tick_rate                              167151874                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      650423                       # Number of instructions simulated
 sim_seconds                                  0.000262                       # Number of seconds simulated
@@ -141,8 +141,24 @@ system.cpu0.icache.writebacks                       0                       # nu
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                          524590                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.num_busy_cycles                    524590                       # Number of busy cycles
+system.cpu0.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu0.num_fp_insts                            0                       # number of float instructions
+system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu0.num_insts                          158353                       # Number of instructions executed
-system.cpu0.num_refs                            73905                       # Number of memory references
+system.cpu0.num_int_alu_accesses               109064                       # Number of integer alu accesses
+system.cpu0.num_int_insts                      109064                       # number of integer instructions
+system.cpu0.num_int_register_reads             315336                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            110671                       # number of times the integer registers were written
+system.cpu0.num_load_insts                      48930                       # Number of load instructions
+system.cpu0.num_mem_refs                        73905                       # number of memory refs
+system.cpu0.num_store_insts                     24975                       # Number of store instructions
 system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses             38632                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_avg_miss_latency 20316.666667                       # average ReadReq miss latency
@@ -279,8 +295,24 @@ system.cpu1.icache.writebacks                       0                       # nu
 system.cpu1.idle_fraction                    0.130715                       # Percentage of idle cycles
 system.cpu1.not_idle_fraction                0.869285                       # Percentage of non-idle cycles
 system.cpu1.numCycles                          513666                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.num_busy_cycles              446521.933500                       # Number of busy cycles
+system.cpu1.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu1.num_fp_insts                            0                       # number of float instructions
+system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu1.num_idle_cycles              67144.066500                       # Number of idle cycles
 system.cpu1.num_insts                          168364                       # Number of instructions executed
-system.cpu1.num_refs                            46919                       # Number of memory references
+system.cpu1.num_int_alu_accesses               105930                       # Number of integer alu accesses
+system.cpu1.num_int_insts                      105930                       # number of integer instructions
+system.cpu1.num_int_register_reads             244134                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes             89763                       # number of times the integer registers were written
+system.cpu1.num_load_insts                      38640                       # Number of load instructions
+system.cpu1.num_mem_refs                        46919                       # number of memory refs
+system.cpu1.num_store_insts                      8279                       # Number of store instructions
 system.cpu2.dcache.ReadReq_accesses             40867                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_avg_miss_latency 15941.935484                       # average ReadReq miss latency
 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 12941.935484                       # average ReadReq mshr miss latency
@@ -416,8 +448,24 @@ system.cpu2.icache.writebacks                       0                       # nu
 system.cpu2.idle_fraction                    0.131215                       # Percentage of idle cycles
 system.cpu2.not_idle_fraction                0.868785                       # Percentage of non-idle cycles
 system.cpu2.numCycles                          513662                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.num_busy_cycles              446261.914218                       # Number of busy cycles
+system.cpu2.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu2.num_fp_insts                            0                       # number of float instructions
+system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu2.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu2.num_idle_cycles              67400.085782                       # Number of idle cycles
 system.cpu2.num_insts                          161536                       # Number of instructions executed
-system.cpu2.num_refs                            56961                       # Number of memory references
+system.cpu2.num_int_alu_accesses               110351                       # Number of integer alu accesses
+system.cpu2.num_int_insts                      110351                       # number of integer instructions
+system.cpu2.num_int_register_reads             284309                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            107647                       # number of times the integer registers were written
+system.cpu2.num_load_insts                      40875                       # Number of load instructions
+system.cpu2.num_mem_refs                        56961                       # number of memory refs
+system.cpu2.num_store_insts                     16086                       # Number of store instructions
 system.cpu3.dcache.ReadReq_accesses             40736                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_avg_miss_latency 16115.384615                       # average ReadReq miss latency
 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13115.384615                       # average ReadReq mshr miss latency
@@ -553,8 +601,24 @@ system.cpu3.icache.writebacks                       0                       # nu
 system.cpu3.idle_fraction                    0.131691                       # Percentage of idle cycles
 system.cpu3.not_idle_fraction                0.868309                       # Percentage of non-idle cycles
 system.cpu3.numCycles                          513670                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.num_busy_cycles              446024.068564                       # Number of busy cycles
+system.cpu3.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu3.num_fp_insts                            0                       # number of float instructions
+system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu3.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu3.num_idle_cycles              67645.931436                       # Number of idle cycles
 system.cpu3.num_insts                          162170                       # Number of instructions executed
-system.cpu3.num_refs                            56264                       # Number of memory references
+system.cpu3.num_int_alu_accesses               110096                       # Number of integer alu accesses
+system.cpu3.num_int_insts                      110096                       # number of integer instructions
+system.cpu3.num_int_register_reads             281520                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            106379                       # number of times the integer registers were written
+system.cpu3.num_load_insts                      40744                       # Number of load instructions
+system.cpu3.num_mem_refs                        56264                       # number of memory refs
+system.cpu3.num_store_insts                     15520                       # Number of store instructions
 system.l2c.ReadExReq_accesses::0                   99                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                   13                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::2                   12                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index 370a5746b..499a69fa0 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
 mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu0]
 type=MemTest
@@ -368,10 +377,9 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
+children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer
 block_size_bytes=64
 clock=1
-debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -383,6 +391,7 @@ tracer=system.ruby.tracer
 
 [system.ruby.cpu_ruby_ports0]
 type=RubySequencer
+access_phys_mem=true
 dcache=system.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.cacheMemory
@@ -395,6 +404,7 @@ port=system.cpu0.test
 
 [system.ruby.cpu_ruby_ports1]
 type=RubySequencer
+access_phys_mem=true
 dcache=system.l1_cntrl1.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl1.cacheMemory
@@ -407,6 +417,7 @@ port=system.cpu1.test
 
 [system.ruby.cpu_ruby_ports2]
 type=RubySequencer
+access_phys_mem=true
 dcache=system.l1_cntrl2.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl2.cacheMemory
@@ -419,6 +430,7 @@ port=system.cpu2.test
 
 [system.ruby.cpu_ruby_ports3]
 type=RubySequencer
+access_phys_mem=true
 dcache=system.l1_cntrl3.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl3.cacheMemory
@@ -431,6 +443,7 @@ port=system.cpu3.test
 
 [system.ruby.cpu_ruby_ports4]
 type=RubySequencer
+access_phys_mem=true
 dcache=system.l1_cntrl4.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl4.cacheMemory
@@ -443,6 +456,7 @@ port=system.cpu4.test
 
 [system.ruby.cpu_ruby_ports5]
 type=RubySequencer
+access_phys_mem=true
 dcache=system.l1_cntrl5.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl5.cacheMemory
@@ -455,6 +469,7 @@ port=system.cpu5.test
 
 [system.ruby.cpu_ruby_ports6]
 type=RubySequencer
+access_phys_mem=true
 dcache=system.l1_cntrl6.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl6.cacheMemory
@@ -467,6 +482,7 @@ port=system.cpu6.test
 
 [system.ruby.cpu_ruby_ports7]
 type=RubySequencer
+access_phys_mem=true
 dcache=system.l1_cntrl7.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl7.cacheMemory
@@ -477,14 +493,6 @@ version=7
 physMemPort=system.physmem.port[7]
 port=system.cpu7.test
 
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
-
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
index f3ddd5354..86ac84392 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
@@ -34,29 +34,29 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Aug/20/2010 13:39:31
+Real time: Feb/07/2011 01:50:48
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 69
-Elapsed_time_in_minutes: 1.15
-Elapsed_time_in_hours: 0.0191667
-Elapsed_time_in_days: 0.000798611
+Elapsed_time_in_seconds: 190
+Elapsed_time_in_minutes: 3.16667
+Elapsed_time_in_hours: 0.0527778
+Elapsed_time_in_days: 0.00219907
 
-Virtual_time_in_seconds: 68.75
-Virtual_time_in_minutes: 1.14583
-Virtual_time_in_hours:   0.0190972
-Virtual_time_in_days:    0.000795718
+Virtual_time_in_seconds: 99.44
+Virtual_time_in_minutes: 1.65733
+Virtual_time_in_hours:   0.0276222
+Virtual_time_in_days:    0.00115093
 
-Ruby_current_time: 11059012
+Ruby_current_time: 57251340
 Ruby_start_time: 0
-Ruby_cycles: 11059012
+Ruby_cycles: 57251340
 
-mbytes_resident: 32.25
-mbytes_total: 333.105
-resident_ratio: 0.0968279
+mbytes_resident: 36.6133
+mbytes_total: 355.375
+resident_ratio: 0.103038
 
-ruby_cycles_executed: [ 11059013 11059013 11059013 11059013 11059013 11059013 11059013 11059013 ]
+ruby_cycles_executed: [ 57251341 57251341 57251341 57251341 57251341 57251341 57251341 57251341 ]
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
@@ -66,31 +66,29 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1228772 average: 1.9375 | standard deviation: 0.242071 | 0 76804 1151968 ]
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1227441 average: 15.9992 | standard deviation: 0.0898992 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1227321 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 4 max: 548 count: 1228757 average: 141.941 | standard deviation: 1.79768 | 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 4 max: 548 count: 798474 average: 141.942 | standard deviation: 1.87927 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 4 max: 459 count: 430283 average: 141.94 | standard deviation: 1.63553 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 3 count: 14 average:     3 | standard deviation: 0 | 0 0 0 14 ]
-miss_latency_Directory: [binsize: 2 max: 359 count: 2 average:   304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_L1Cache_wCC: [binsize: 4 max: 548 count: 1228741 average: 141.942 | standard deviation: 1.72165 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average:     0 | standard deviation: 0 | 6 ]
-miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average:     0 | standard deviation: 0 | 6 ]
-miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average:     0 | standard deviation: 0 | 6 ]
-miss_latency_wCC_first_response_to_completion: [binsize: 4 max: 495 count: 6 average: 412.667 | standard deviation: 76.4147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-imcomplete_wCC_Times: 1228735
-miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average:     0 | standard deviation: 0 | 2 ]
-miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average:     0 | standard deviation: 0 | 2 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average:     0 | standard deviation: 0 | 2 ]
-miss_latency_dir_first_response_to_completion: [binsize: 2 max: 359 count: 2 average:   304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-imcomplete_dir_Times: 0
-miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 7 average:     3 | standard deviation: 0 | 0 0 0 7 ]
-miss_latency_LD_Directory: [binsize: 2 max: 359 count: 2 average:   304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 548 count: 798465 average: 141.943 | standard deviation: 1.81358 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 7 average:     3 | standard deviation: 0 | 0 0 0 7 ]
-miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 459 count: 430276 average: 141.942 | standard deviation: 1.53653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 128 max: 16170 count: 1227313 average: 5970.6 | standard deviation: 6226.1 | 0 5 5 5 5 5 5 5 3 0 6 5 4 9 28 67 117 196 325 493 850 1372 2115 2889 3474 5267 7331 8923 10961 13117 17439 19106 22197 27797 27598 30754 34950 40376 40150 37193 44218 47799 45035 44430 44397 47887 43214 42194 45299 37620 36866 36136 37155 31716 26415 28478 27184 22299 20319 18521 18170 14600 13557 13481 10233 9188 8568 8384 6564 5202 5341 4736 3697 3355 2785 2534 2139 1813 1715 1305 1213 1037 977 761 540 516 459 368 287 221 221 156 133 132 101 86 57 64 45 25 28 41 28 25 18 17 8 7 9 7 4 5 8 3 2 0 0 1 0 2 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 128 max: 16170 count: 797864 average: 5970.96 | standard deviation: 5567.96 | 0 4 4 4 4 4 4 4 1 0 1 4 4 6 23 42 79 125 214 331 544 877 1397 1863 2231 3466 4741 5801 7112 8516 11461 12380 14439 17894 17955 19944 22577 26201 26233 24153 28751 31184 29257 28993 28655 31123 28291 27538 29428 24371 23978 23499 24308 20557 17139 18652 17606 14368 13155 11966 11765 9607 8837 8844 6659 5936 5560 5504 4210 3414 3473 3145 2395 2145 1816 1622 1380 1171 1141 849 772 673 638 482 346 347 309 240 185 140 136 95 84 85 65 59 40 42 31 15 21 23 20 16 13 11 6 3 6 5 3 3 6 3 1 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 128 max: 15290 count: 429449 average: 5969.93 | standard deviation: 1423.42 | 0 1 1 1 1 1 1 1 2 0 5 1 0 3 5 25 38 71 111 162 306 495 718 1026 1243 1801 2590 3122 3849 4601 5978 6726 7758 9903 9643 10810 12373 14175 13917 13040 15467 16615 15778 15437 15742 16764 14923 14656 15871 13249 12888 12637 12847 11159 9276 9826 9578 7931 7164 6555 6405 4993 4720 4637 3574 3252 3008 2880 2354 1788 1868 1591 1302 1210 969 912 759 642 574 456 441 364 339 279 194 169 150 128 102 81 85 61 49 47 36 27 17 22 14 10 7 18 8 9 5 6 2 4 3 2 1 2 2 0 1 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 128 max: 16170 count: 1210799 average: 5976.91 | standard deviation: 6306.43 | 0 5 5 5 5 5 5 5 3 0 6 5 4 9 25 62 110 189 305 465 806 1312 2035 2792 3339 5094 7111 8663 10701 12775 17023 18729 21808 27255 27055 30221 34375 39759 39511 36575 43613 47122 44479 43852 43802 47301 42687 41791 44754 37147 36463 35788 36800 31395 26170 28198 26928 22083 20141 18352 18010 14477 13445 13354 10138 9095 8497 8327 6511 5159 5306 4695 3671 3321 2764 2511 2121 1803 1701 1296 1209 1028 975 758 537 511 458 365 284 218 218 156 133 132 101 86 57 62 43 25 28 41 28 25 18 17 8 7 9 7 4 5 8 3 2 0 0 1 0 2 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache_wCC: [binsize: 64 max: 12585 count: 16514 average: 5507.92 | standard deviation: 1405.44 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 3 2 3 4 3 4 10 10 16 12 19 25 26 34 35 45 45 52 71 64 84 89 98 122 124 136 137 123 165 177 197 219 187 190 187 202 274 268 276 267 243 290 258 317 297 320 337 302 325 293 290 315 320 357 281 275 296 282 331 264 270 316 252 275 203 200 297 248 265 208 206 197 170 178 187 168 186 135 131 114 140 140 129 127 114 102 100 78 86 83 72 88 56 67 54 58 72 55 56 39 45 48 44 27 26 31 22 31 24 19 19 16 27 14 14 12 24 10 13 8 8 15 10 8 4 6 9 5 3 6 2 2 2 7 1 1 0 3 1 2 3 2 0 1 2 1 2 1 2 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 16514
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 8 average:     0 | standard deviation: 0 | 8 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 8 average:     0 | standard deviation: 0 | 8 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 8 average:     0 | standard deviation: 0 | 8 ]
+miss_latency_dir_first_response_to_completion: [binsize: 4 max: 569 count: 8 average: 330.25 | standard deviation: 178.281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+imcomplete_dir_Times: 1210791
+miss_latency_LD_Directory: [binsize: 128 max: 16170 count: 787157 average: 5977.4 | standard deviation: 5638.59 | 0 4 4 4 4 4 4 4 1 0 1 4 4 6 20 37 73 120 198 310 520 832 1338 1800 2148 3355 4608 5614 6946 8289 11207 12142 14179 17561 17587 19588 22210 25807 25824 23747 28369 30735 28910 28603 28263 30729 27952 27268 29067 24058 23732 23284 24091 20357 16975 18458 17439 14222 13051 11864 11662 9526 8758 8751 6596 5876 5513 5476 4177 3395 3452 3117 2376 2125 1802 1609 1370 1164 1131 844 770 668 638 481 345 344 308 238 182 138 133 95 84 85 65 59 40 42 31 15 21 23 20 16 13 11 6 3 6 5 3 3 6 3 1 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 64 max: 11604 count: 10707 average: 5497.29 | standard deviation: 1398.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 3 2 2 4 2 3 10 6 11 10 12 12 21 24 26 33 30 33 43 40 49 62 62 71 90 97 85 81 109 118 117 137 123 115 124 136 167 166 175 193 160 196 158 209 187 207 224 185 212 194 180 202 215 234 180 167 201 189 218 174 184 210 163 176 141 129 197 164 169 144 128 118 105 110 104 113 120 80 90 74 101 93 83 84 71 75 61 43 49 53 49 54 38 43 42 37 49 44 36 27 27 33 26 21 9 19 11 22 10 9 12 9 20 8 11 8 14 6 9 5 6 7 5 5 4 3 6 4 3 2 1 1 1 4 0 0 0 1 0 1 2 1 0 1 2 0 2 1 2 0 1 2 ]
+miss_latency_ST_Directory: [binsize: 128 max: 15290 count: 423642 average:  5976 | standard deviation: 1422.53 | 0 1 1 1 1 1 1 1 2 0 5 1 0 3 5 25 37 69 107 155 286 480 697 992 1191 1739 2503 3049 3755 4486 5816 6587 7629 9694 9468 10633 12165 13952 13687 12828 15244 16387 15569 15249 15539 16572 14735 14523 15687 13089 12731 12504 12709 11038 9195 9740 9489 7861 7090 6488 6348 4951 4687 4603 3542 3219 2984 2851 2334 1764 1854 1578 1295 1196 962 902 751 639 570 452 439 360 337 277 192 167 150 127 102 80 85 61 49 47 36 27 17 20 12 10 7 18 8 9 5 6 2 4 3 2 1 2 2 0 1 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 64 max: 12585 count: 5807 average: 5527.52 | standard deviation: 1418.56 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 4 5 2 7 13 5 10 9 12 15 19 28 24 35 27 36 51 34 39 52 42 56 59 80 82 64 75 63 66 107 102 101 74 83 94 100 108 110 113 113 117 113 99 110 113 105 123 101 108 95 93 113 90 86 106 89 99 62 71 100 84 96 64 78 79 65 68 83 55 66 55 41 40 39 47 46 43 43 27 39 35 37 30 23 34 18 24 12 21 23 11 20 12 18 15 18 6 17 12 11 9 14 10 7 7 7 6 3 4 10 4 4 3 2 8 5 3 0 3 3 1 0 4 1 1 1 3 1 1 0 2 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -104,11 +102,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
 
 Message Delayed Cycles
 ----------------------
-Total_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
-Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
+Total_delay_cycles: [binsize: 1 max: 18 count: 2458515 average: 0.000321739 | standard deviation: 0.0752325 | 2458470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 26 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 2458515 average: 0.000321739 | standard deviation: 0.0752325 | 2458470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 26 ]
   virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1228743 average:     0 | standard deviation: 0 | 1228743 ]
-  virtual_network_2_delay_cycles: [binsize: 4 max: 151 count: 1228743 average: 94.9391 | standard deviation: 1.44451 | 2 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1227313 average:     0 | standard deviation: 0 | 1227313 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 18 count: 1231202 average: 0.000642462 | standard deviation: 0.106311 | 1231157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 26 ]
   virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -120,326 +118,337 @@ Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 |
 Resource Usage
 --------------
 page_size: 4096
-user_time: 68
+user_time: 99
 system_time: 0
-page_reclaims: 9322
+page_reclaims: 10455
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 112
 
 Network Stats
 -------------
 
-total_msg_count_Control: 3686271 29490168
-total_msg_count_Response_Data: 3686229 265408488
-total_msg_count_Writeback_Control: 3686259 29490072
-total_msgs: 11058759 total_bytes: 324388728
+total_msg_count_Control: 3681972 29455776
+total_msg_count_Data: 3644124 262376928
+total_msg_count_Response_Data: 3681939 265099608
+total_msg_count_Writeback_Control: 3693606 29548848
+total_msgs: 14701641 total_bytes: 586481160
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.434016
-  links_utilized_percent_switch_0_link_0: 0.173606 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.694426 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.083792
+  links_utilized_percent_switch_0_link_0: 0.0334493 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.134135 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 153153 11027016 [ 0 0 0 0 153153 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 153635 1229080 [ 0 0 0 153635 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 153154 1225232 [ 0 0 153154 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Data: 151525 10909800 [ 0 0 151525 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 2111 151992 [ 0 0 0 0 2111 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.434016
-  links_utilized_percent_switch_1_link_0: 0.173606 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.694426 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.0839004
+  links_utilized_percent_switch_1_link_0: 0.0334929 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.134308 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Data: 153353 11041416 [ 0 0 0 0 153353 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Control: 153833 1230664 [ 0 0 0 153833 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Control: 153355 1226840 [ 0 0 153355 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Data: 151790 10928880 [ 0 0 151790 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 2044 147168 [ 0 0 0 0 2044 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.434016
-  links_utilized_percent_switch_2_link_0: 0.173606 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.694426 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.0839292
+  links_utilized_percent_switch_2_link_0: 0.0334995 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.134359 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_2_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 153380 11043360 [ 0 0 0 0 153380 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 153895 1231160 [ 0 0 0 153895 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 153381 1227048 [ 0 0 153381 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Data: 151808 10930176 [ 0 0 151808 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 2088 150336 [ 0 0 0 0 2088 0 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 2
 switch_3_outlinks: 2
-links_utilized_percent_switch_3: 0.434016
-  links_utilized_percent_switch_3_link_0: 0.173606 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 0.694426 bw: 160000 base_latency: 1
+links_utilized_percent_switch_3: 0.0839178
+  links_utilized_percent_switch_3_link_0: 0.0335004 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 0.134335 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_3_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 153388 11043936 [ 0 0 0 0 153388 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Control: 153864 1230912 [ 0 0 0 153864 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Control: 153389 1227112 [ 0 0 153389 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Data: 151791 10928952 [ 0 0 151791 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 2074 149328 [ 0 0 0 0 2074 0 0 0 0 0 ] base_latency: 1
 
 switch_4_inlinks: 2
 switch_4_outlinks: 2
-links_utilized_percent_switch_4: 0.434014
-  links_utilized_percent_switch_4_link_0: 0.173606 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_4_link_1: 0.694421 bw: 160000 base_latency: 1
+links_utilized_percent_switch_4: 0.0841195
+  links_utilized_percent_switch_4_link_0: 0.0335808 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 0.134658 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_4_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Data: 153756 11070432 [ 0 0 0 0 153756 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Control: 154232 1233856 [ 0 0 0 154232 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Control: 153758 1230064 [ 0 0 153758 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Data: 152172 10956384 [ 0 0 152172 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 2063 148536 [ 0 0 0 0 2063 0 0 0 0 0 ] base_latency: 1
 
 switch_5_inlinks: 2
 switch_5_outlinks: 2
-links_utilized_percent_switch_5: 0.434016
-  links_utilized_percent_switch_5_link_0: 0.173606 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_5_link_1: 0.694426 bw: 160000 base_latency: 1
+links_utilized_percent_switch_5: 0.0840452
+  links_utilized_percent_switch_5_link_0: 0.0335493 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 0.134541 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_5_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Data: 153611 11059992 [ 0 0 0 0 153611 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Writeback_Control: 154097 1232776 [ 0 0 0 154097 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Control: 153613 1228904 [ 0 0 153613 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Data: 152110 10951920 [ 0 0 152110 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 1992 143424 [ 0 0 0 0 1992 0 0 0 0 0 ] base_latency: 1
 
 switch_6_inlinks: 2
 switch_6_outlinks: 2
-links_utilized_percent_switch_6: 0.434014
-  links_utilized_percent_switch_6_link_0: 0.173606 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_6_link_1: 0.694421 bw: 160000 base_latency: 1
+links_utilized_percent_switch_6: 0.084233
+  links_utilized_percent_switch_6_link_0: 0.0336256 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 0.13484 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_6_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Data: 153961 11085192 [ 0 0 0 0 153961 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Writeback_Control: 154441 1235528 [ 0 0 0 154441 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Control: 153962 1231696 [ 0 0 153962 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Data: 152406 10973232 [ 0 0 152406 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 2038 146736 [ 0 0 0 0 2038 0 0 0 0 0 ] base_latency: 1
 
 switch_7_inlinks: 2
 switch_7_outlinks: 2
-links_utilized_percent_switch_7: 0.434013
-  links_utilized_percent_switch_7_link_0: 0.173605 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_7_link_1: 0.694421 bw: 160000 base_latency: 1
+links_utilized_percent_switch_7: 0.0835571
+  links_utilized_percent_switch_7_link_0: 0.033353 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 0.133761 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_7_link_0_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Data: 152711 10995192 [ 0 0 0 0 152711 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Control: 153205 1225640 [ 0 0 0 153205 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Control: 152712 1221696 [ 0 0 152712 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Data: 151106 10879632 [ 0 0 151106 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 2104 151488 [ 0 0 0 0 2104 0 0 0 0 0 ] base_latency: 1
 
 switch_8_inlinks: 2
 switch_8_outlinks: 2
-links_utilized_percent_switch_8: 0.347219
-  links_utilized_percent_switch_8_link_0: 0.138886 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_8_link_1: 0.555552 bw: 160000 base_latency: 1
+links_utilized_percent_switch_8: 0.662356
+  links_utilized_percent_switch_8_link_0: 0.265489 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 1.05922 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_8_link_0_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Control: 1228753 9830024 [ 0 0 0 1228753 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Control: 1227324 9818592 [ 0 0 1227324 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Data: 1214708 87458976 [ 0 0 1214708 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 1210799 87177528 [ 0 0 0 0 1210799 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Control: 1231202 9849616 [ 0 0 0 1231202 0 0 0 0 0 0 ] base_latency: 1
 
 switch_9_inlinks: 9
 switch_9_outlinks: 9
-links_utilized_percent_switch_9: 0.678994
-  links_utilized_percent_switch_9_link_0: 0.694425 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_1: 0.694425 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_2: 0.694426 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_3: 0.694425 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_4: 0.694425 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_5: 0.694425 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_6: 0.694425 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_7: 0.694421 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_8: 0.555546 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_9_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_9: 0.237129
+  links_utilized_percent_switch_9_link_0: 0.133797 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 0.133972 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_2: 0.133998 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_3: 0.134002 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_4: 0.134323 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_5: 0.134197 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_6: 0.134503 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_7: 0.133412 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_8: 1.06196 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Response_Data: 153153 11027016 [ 0 0 0 0 153153 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Control: 153635 1229080 [ 0 0 0 153635 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 153353 11041416 [ 0 0 0 0 153353 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Control: 153833 1230664 [ 0 0 0 153833 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Data: 153380 11043360 [ 0 0 0 0 153380 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Writeback_Control: 153895 1231160 [ 0 0 0 153895 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Data: 153388 11043936 [ 0 0 0 0 153388 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Writeback_Control: 153864 1230912 [ 0 0 0 153864 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Data: 153756 11070432 [ 0 0 0 0 153756 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Writeback_Control: 154232 1233856 [ 0 0 0 154232 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Data: 153611 11059992 [ 0 0 0 0 153611 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Writeback_Control: 154097 1232776 [ 0 0 0 154097 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Data: 153961 11085192 [ 0 0 0 0 153961 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Writeback_Control: 154441 1235528 [ 0 0 0 154441 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Data: 152711 10995192 [ 0 0 0 0 152711 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Writeback_Control: 153205 1225640 [ 0 0 0 153205 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Control: 1227324 9818592 [ 0 0 1227324 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Data: 1214708 87458976 [ 0 0 1214708 0 0 0 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.cacheMemory
-  system.l1_cntrl0.cacheMemory_total_misses: 153595
-  system.l1_cntrl0.cacheMemory_total_demand_misses: 153595
+  system.l1_cntrl0.cacheMemory_total_misses: 153154
+  system.l1_cntrl0.cacheMemory_total_demand_misses: 153154
   system.l1_cntrl0.cacheMemory_total_prefetches: 0
   system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.cacheMemory_request_type_LD:   64.8608%
-  system.l1_cntrl0.cacheMemory_request_type_ST:   35.1392%
+  system.l1_cntrl0.cacheMemory_request_type_LD:   65.2232%
+  system.l1_cntrl0.cacheMemory_request_type_ST:   34.7768%
 
-  system.l1_cntrl0.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
+  system.l1_cntrl0.cacheMemory_access_mode_type_SupervisorMode:   153154    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [100001 99948 99718 99978 99623 99719 99984 99512 ] 798483
+Load [99856 100002 99839 99184 99892 99648 99764 99685 ] 797870
 Ifetch [0 0 0 0 0 0 0 0 ] 0
-Store [53593 53647 53876 53616 53974 53880 53619 54083 ] 430288
-Data [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743
-Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743
+Store [53902 53611 54123 53528 53262 53707 53617 53704 ] 429454
+Data [153756 153611 153961 152711 153153 153353 153380 153388 ] 1227313
+Fwd_GETX [2063 1992 2038 2104 2111 2044 2088 2074 ] 16514
 Inv [0 0 0 0 0 0 0 0 ] 0
-Replacement [0 0 0 0 0 0 0 0 ] 0
-Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
-Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
+Replacement [153754 153609 153958 152708 153150 153351 153377 153385 ] 1227292
+Writeback_Ack [151688 151612 151917 150599 151038 151306 151288 151310 ] 1210758
+Writeback_Nack [481 493 486 502 486 483 519 480 ] 3930
 
  - Transitions -
-I  Load [100001 99948 99718 99978 99623 99718 99978 99512 ] 798476
+I  Load [99856 100002 99839 99184 99892 99648 99764 99685 ] 797870
 I  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I  Store [53593 53647 53876 53616 53972 53877 53617 54083 ] 430281
+I  Store [53902 53611 54123 53528 53262 53707 53617 53704 ] 429454
 I  Inv [0 0 0 0 0 0 0 0 ] 0
-I  Replacement [0 0 0 0 0 0 0 0 ] 0
+I  Replacement [1582 1499 1552 1602 1625 1561 1569 1594 ] 12584
 
-II  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
+II  Writeback_Nack [481 493 486 502 486 483 519 480 ] 3930
 
-M  Load [0 0 0 0 0 1 6 0 ] 7
+M  Load [0 0 0 0 0 0 0 0 ] 0
 M  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M  Store [0 0 0 0 2 3 2 0 ] 7
-M  Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743
+M  Store [0 0 0 0 0 0 0 0 ] 0
+M  Fwd_GETX [1582 1499 1552 1602 1625 1561 1569 1594 ] 12584
 M  Inv [0 0 0 0 0 0 0 0 ] 0
-M  Replacement [0 0 0 0 0 0 0 0 ] 0
+M  Replacement [152172 152110 152406 151106 151525 151790 151808 151791 ] 1214708
 
-MI  Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
+MI  Fwd_GETX [481 493 486 502 486 483 519 480 ] 3930
 MI  Inv [0 0 0 0 0 0 0 0 ] 0
-MI  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
+MI  Writeback_Ack [151688 151612 151917 150599 151038 151306 151288 151310 ] 1210758
 MI  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 
 MII  Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
 
-IS  Data [100000 99946 99718 99976 99622 99716 99977 99512 ] 798467
+IS  Data [99856 100000 99838 99183 99892 99647 99764 99684 ] 797864
 
-IM  Data [53593 53647 53875 53616 53971 53877 53616 54081 ] 430276
+IM  Data [53900 53611 54123 53528 53261 53706 53616 53704 ] 429449
 
 Cache Stats: system.l1_cntrl1.cacheMemory
-  system.l1_cntrl1.cacheMemory_total_misses: 153595
-  system.l1_cntrl1.cacheMemory_total_demand_misses: 153595
+  system.l1_cntrl1.cacheMemory_total_misses: 153355
+  system.l1_cntrl1.cacheMemory_total_demand_misses: 153355
   system.l1_cntrl1.cacheMemory_total_prefetches: 0
   system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.cacheMemory_request_type_LD:   64.9227%
-  system.l1_cntrl1.cacheMemory_request_type_ST:   35.0773%
+  system.l1_cntrl1.cacheMemory_request_type_LD:   64.9786%
+  system.l1_cntrl1.cacheMemory_request_type_ST:   35.0214%
 
-  system.l1_cntrl1.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
+  system.l1_cntrl1.cacheMemory_access_mode_type_SupervisorMode:   153355    100%
 
 Cache Stats: system.l1_cntrl2.cacheMemory
-  system.l1_cntrl2.cacheMemory_total_misses: 153595
-  system.l1_cntrl2.cacheMemory_total_demand_misses: 153595
+  system.l1_cntrl2.cacheMemory_total_misses: 153381
+  system.l1_cntrl2.cacheMemory_total_demand_misses: 153381
   system.l1_cntrl2.cacheMemory_total_prefetches: 0
   system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.cacheMemory_request_type_LD:   65.092%
-  system.l1_cntrl2.cacheMemory_request_type_ST:   34.908%
+  system.l1_cntrl2.cacheMemory_request_type_LD:   65.0433%
+  system.l1_cntrl2.cacheMemory_request_type_ST:   34.9567%
 
-  system.l1_cntrl2.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
+  system.l1_cntrl2.cacheMemory_access_mode_type_SupervisorMode:   153381    100%
 
 Cache Stats: system.l1_cntrl3.cacheMemory
-  system.l1_cntrl3.cacheMemory_total_misses: 153595
-  system.l1_cntrl3.cacheMemory_total_demand_misses: 153595
+  system.l1_cntrl3.cacheMemory_total_misses: 153389
+  system.l1_cntrl3.cacheMemory_total_demand_misses: 153389
   system.l1_cntrl3.cacheMemory_total_prefetches: 0
   system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.cacheMemory_request_type_LD:   64.7886%
-  system.l1_cntrl3.cacheMemory_request_type_ST:   35.2114%
+  system.l1_cntrl3.cacheMemory_request_type_LD:   64.9884%
+  system.l1_cntrl3.cacheMemory_request_type_ST:   35.0116%
 
-  system.l1_cntrl3.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
+  system.l1_cntrl3.cacheMemory_access_mode_type_SupervisorMode:   153389    100%
 
 Cache Stats: system.l1_cntrl4.cacheMemory
-  system.l1_cntrl4.cacheMemory_total_misses: 153594
-  system.l1_cntrl4.cacheMemory_total_demand_misses: 153594
+  system.l1_cntrl4.cacheMemory_total_misses: 153758
+  system.l1_cntrl4.cacheMemory_total_demand_misses: 153758
   system.l1_cntrl4.cacheMemory_total_prefetches: 0
   system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.cacheMemory_request_type_LD:   65.1074%
-  system.l1_cntrl4.cacheMemory_request_type_ST:   34.8926%
+  system.l1_cntrl4.cacheMemory_request_type_LD:   64.9436%
+  system.l1_cntrl4.cacheMemory_request_type_ST:   35.0564%
 
-  system.l1_cntrl4.cacheMemory_access_mode_type_SupervisorMode:   153594    100%
+  system.l1_cntrl4.cacheMemory_access_mode_type_SupervisorMode:   153758    100%
 
 Cache Stats: system.l1_cntrl5.cacheMemory
-  system.l1_cntrl5.cacheMemory_total_misses: 153595
-  system.l1_cntrl5.cacheMemory_total_demand_misses: 153595
+  system.l1_cntrl5.cacheMemory_total_misses: 153613
+  system.l1_cntrl5.cacheMemory_total_demand_misses: 153613
   system.l1_cntrl5.cacheMemory_total_prefetches: 0
   system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.cacheMemory_request_type_LD:   65.0724%
-  system.l1_cntrl5.cacheMemory_request_type_ST:   34.9276%
+  system.l1_cntrl5.cacheMemory_request_type_LD:   65.1%
+  system.l1_cntrl5.cacheMemory_request_type_ST:   34.9%
 
-  system.l1_cntrl5.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
+  system.l1_cntrl5.cacheMemory_access_mode_type_SupervisorMode:   153613    100%
 
 Cache Stats: system.l1_cntrl6.cacheMemory
-  system.l1_cntrl6.cacheMemory_total_misses: 153594
-  system.l1_cntrl6.cacheMemory_total_demand_misses: 153594
+  system.l1_cntrl6.cacheMemory_total_misses: 153962
+  system.l1_cntrl6.cacheMemory_total_demand_misses: 153962
   system.l1_cntrl6.cacheMemory_total_prefetches: 0
   system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.cacheMemory_request_type_LD:   64.9231%
-  system.l1_cntrl6.cacheMemory_request_type_ST:   35.0769%
+  system.l1_cntrl6.cacheMemory_request_type_LD:   64.8465%
+  system.l1_cntrl6.cacheMemory_request_type_ST:   35.1535%
 
-  system.l1_cntrl6.cacheMemory_access_mode_type_SupervisorMode:   153594    100%
+  system.l1_cntrl6.cacheMemory_access_mode_type_SupervisorMode:   153962    100%
 
 Cache Stats: system.l1_cntrl7.cacheMemory
-  system.l1_cntrl7.cacheMemory_total_misses: 153594
-  system.l1_cntrl7.cacheMemory_total_demand_misses: 153594
+  system.l1_cntrl7.cacheMemory_total_misses: 152712
+  system.l1_cntrl7.cacheMemory_total_demand_misses: 152712
   system.l1_cntrl7.cacheMemory_total_prefetches: 0
   system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.cacheMemory_request_type_LD:   65.0924%
-  system.l1_cntrl7.cacheMemory_request_type_ST:   34.9076%
+  system.l1_cntrl7.cacheMemory_request_type_LD:   64.9484%
+  system.l1_cntrl7.cacheMemory_request_type_ST:   35.0516%
 
-  system.l1_cntrl7.cacheMemory_access_mode_type_SupervisorMode:   153594    100%
+  system.l1_cntrl7.cacheMemory_access_mode_type_SupervisorMode:   152712    100%
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 2
-  memory_reads: 2
-  memory_writes: 0
-  memory_refreshes: 22
-  memory_total_request_delays: 31
-  memory_delays_per_request: 15.5
-  memory_delays_in_input_queue: 1
-  memory_delays_behind_head_of_bank_queue: 10
-  memory_delays_stalled_at_head_of_bank_queue: 20
-  memory_stalls_for_bank_busy: 20
+  memory_total_requests: 2421588
+  memory_reads: 1210803
+  memory_writes: 1210758
+  memory_refreshes: 119274
+  memory_total_request_delays: 190155514
+  memory_delays_per_request: 78.5251
+  memory_delays_in_input_queue: 11307810
+  memory_delays_behind_head_of_bank_queue: 85310074
+  memory_delays_stalled_at_head_of_bank_queue: 93537630
+  memory_stalls_for_bank_busy: 14384463
   memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 0
-  memory_stalls_for_bus: 0
+  memory_stalls_for_anti_starvation: 24076432
+  memory_stalls_for_arbitration: 18499124
+  memory_stalls_for_bus: 25289267
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 0
-  memory_stalls_for_read_read_turnaround: 0
-  accesses_per_bank: 2  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  
+  memory_stalls_for_read_write_turnaround: 9173208
+  memory_stalls_for_read_read_turnaround: 2115136
+  accesses_per_bank: 75973  75871  75584  75990  75871  76208  76264  75323  76082  76056  76271  75892  75688  75751  75586  75406  75587  75216  76023  75699  75573  75534  75382  75564  75891  75161  75298  74700  75598  75166  76030  75350  
 
  --- Directory ---
  - Event Counts -
-GETX [1229168 ] 1229168
+GETX [2497405 ] 2497405
 GETS [0 ] 0
-PUTX [0 ] 0
-PUTX_NotOwner [0 ] 0
+PUTX [1210778 ] 1210778
+PUTX_NotOwner [3930 ] 3930
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
-Memory_Data [2 ] 2
-Memory_Ack [0 ] 0
+Memory_Data [1210799 ] 1210799
+Memory_Ack [1210758 ] 1210758
 
  - Transitions -
-I  GETX [2 ] 2
+I  GETX [1210810 ] 1210810
 I  PUTX_NotOwner [0 ] 0
 I  DMA_READ [0 ] 0
 I  DMA_WRITE [0 ] 0
 
-M  GETX [1228755 ] 1228755
-M  PUTX [0 ] 0
-M  PUTX_NotOwner [0 ] 0
+M  GETX [16514 ] 16514
+M  PUTX [1210778 ] 1210778
+M  PUTX_NotOwner [3930 ] 3930
 M  DMA_READ [0 ] 0
 M  DMA_WRITE [0 ] 0
 
@@ -455,21 +464,21 @@ M_DWRI  Memory_Ack [0 ] 0
 M_DRDI  GETX [0 ] 0
 M_DRDI  Memory_Ack [0 ] 0
 
-IM  GETX [411 ] 411
+IM  GETX [491344 ] 491344
 IM  GETS [0 ] 0
 IM  PUTX [0 ] 0
 IM  PUTX_NotOwner [0 ] 0
 IM  DMA_READ [0 ] 0
 IM  DMA_WRITE [0 ] 0
-IM  Memory_Data [2 ] 2
+IM  Memory_Data [1210799 ] 1210799
 
-MI  GETX [0 ] 0
+MI  GETX [778737 ] 778737
 MI  GETS [0 ] 0
 MI  PUTX [0 ] 0
 MI  PUTX_NotOwner [0 ] 0
 MI  DMA_READ [0 ] 0
 MI  DMA_WRITE [0 ] 0
-MI  Memory_Ack [0 ] 0
+MI  Memory_Ack [1210758 ] 1210758
 
 ID  GETX [0 ] 0
 ID  GETS [0 ] 0
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
index bc0af1811..e2711df60 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -1,74 +1,74 @@
-system.cpu5: completed 10000 read accesses @1097056
-system.cpu4: completed 10000 read accesses @1101790
-system.cpu2: completed 10000 read accesses @1104058
-system.cpu0: completed 10000 read accesses @1107910
-system.cpu7: completed 10000 read accesses @1111870
-system.cpu1: completed 10000 read accesses @1114192
-system.cpu6: completed 10000 read accesses @1114876
-system.cpu3: completed 10000 read accesses @1117090
-system.cpu5: completed 20000 read accesses @2192968
-system.cpu0: completed 20000 read accesses @2201554
-system.cpu2: completed 20000 read accesses @2213290
-system.cpu4: completed 20000 read accesses @2213470
-system.cpu6: completed 20000 read accesses @2213812
-system.cpu7: completed 20000 read accesses @2222758
-system.cpu1: completed 20000 read accesses @2232856
-system.cpu3: completed 20000 read accesses @2238562
-system.cpu5: completed 30000 read accesses @3309256
-system.cpu6: completed 30000 read accesses @3313180
-system.cpu0: completed 30000 read accesses @3314566
-system.cpu4: completed 30000 read accesses @3316942
-system.cpu2: completed 30000 read accesses @3324682
-system.cpu7: completed 30000 read accesses @3331702
-system.cpu1: completed 30000 read accesses @3337912
-system.cpu3: completed 30000 read accesses @3342322
-system.cpu5: completed 40000 read accesses @4420792
-system.cpu7: completed 40000 read accesses @4420990
-system.cpu6: completed 40000 read accesses @4421692
-system.cpu4: completed 40000 read accesses @4422430
-system.cpu0: completed 40000 read accesses @4424770
-system.cpu2: completed 40000 read accesses @4424842
-system.cpu3: completed 40000 read accesses @4446316
-system.cpu1: completed 40000 read accesses @4448440
-system.cpu5: completed 50000 read accesses @5519584
-system.cpu4: completed 50000 read accesses @5528980
-system.cpu0: completed 50000 read accesses @5530150
-system.cpu2: completed 50000 read accesses @5533210
-system.cpu7: completed 50000 read accesses @5537782
-system.cpu6: completed 50000 read accesses @5538916
-system.cpu3: completed 50000 read accesses @5549410
-system.cpu1: completed 50000 read accesses @5549536
-system.cpu7: completed 60000 read accesses @6629734
-system.cpu5: completed 60000 read accesses @6636160
-system.cpu4: completed 60000 read accesses @6637060
-system.cpu2: completed 60000 read accesses @6637402
-system.cpu0: completed 60000 read accesses @6644710
-system.cpu1: completed 60000 read accesses @6651352
-system.cpu6: completed 60000 read accesses @6651892
-system.cpu3: completed 60000 read accesses @6661234
-system.cpu7: completed 70000 read accesses @7727014
-system.cpu4: completed 70000 read accesses @7730110
-system.cpu5: completed 70000 read accesses @7736608
-system.cpu2: completed 70000 read accesses @7742746
-system.cpu6: completed 70000 read accesses @7757092
-system.cpu0: completed 70000 read accesses @7759378
-system.cpu1: completed 70000 read accesses @7770088
-system.cpu3: completed 70000 read accesses @7773058
-system.cpu5: completed 80000 read accesses @8842240
-system.cpu7: completed 80000 read accesses @8843086
-system.cpu4: completed 80000 read accesses @8844580
-system.cpu2: completed 80000 read accesses @8853131
-system.cpu0: completed 80000 read accesses @8863426
-system.cpu6: completed 80000 read accesses @8876836
-system.cpu1: completed 80000 read accesses @8878960
-system.cpu3: completed 80000 read accesses @8885602
-system.cpu5: completed 90000 read accesses @9955126
-system.cpu7: completed 90000 read accesses @9956782
-system.cpu4: completed 90000 read accesses @9957844
-system.cpu2: completed 90000 read accesses @9967690
-system.cpu1: completed 90000 read accesses @9973576
-system.cpu0: completed 90000 read accesses @9976024
-system.cpu6: completed 90000 read accesses @9981604
-system.cpu3: completed 90000 read accesses @9999874
-system.cpu4: completed 100000 read accesses @11059012
+system.cpu5: completed 10000 read accesses @5727250
+system.cpu4: completed 10000 read accesses @5731690
+system.cpu7: completed 10000 read accesses @5735040
+system.cpu3: completed 10000 read accesses @5738300
+system.cpu6: completed 10000 read accesses @5748590
+system.cpu2: completed 10000 read accesses @5761080
+system.cpu0: completed 10000 read accesses @5773280
+system.cpu1: completed 10000 read accesses @5776650
+system.cpu4: completed 20000 read accesses @11398130
+system.cpu1: completed 20000 read accesses @11455110
+system.cpu3: completed 20000 read accesses @11459820
+system.cpu6: completed 20000 read accesses @11463230
+system.cpu0: completed 20000 read accesses @11469310
+system.cpu5: completed 20000 read accesses @11490080
+system.cpu2: completed 20000 read accesses @11498750
+system.cpu7: completed 20000 read accesses @11572610
+system.cpu4: completed 30000 read accesses @17076120
+system.cpu1: completed 30000 read accesses @17150670
+system.cpu5: completed 30000 read accesses @17204690
+system.cpu3: completed 30000 read accesses @17209580
+system.cpu0: completed 30000 read accesses @17264545
+system.cpu6: completed 30000 read accesses @17274220
+system.cpu2: completed 30000 read accesses @17284860
+system.cpu7: completed 30000 read accesses @17343350
+system.cpu4: completed 40000 read accesses @22747010
+system.cpu1: completed 40000 read accesses @22900920
+system.cpu5: completed 40000 read accesses @22928450
+system.cpu3: completed 40000 read accesses @22962360
+system.cpu0: completed 40000 read accesses @22981310
+system.cpu6: completed 40000 read accesses @23018750
+system.cpu2: completed 40000 read accesses @23061180
+system.cpu7: completed 40000 read accesses @23154824
+system.cpu4: completed 50000 read accesses @28547090
+system.cpu5: completed 50000 read accesses @28620310
+system.cpu1: completed 50000 read accesses @28677730
+system.cpu3: completed 50000 read accesses @28690730
+system.cpu6: completed 50000 read accesses @28729220
+system.cpu0: completed 50000 read accesses @28766380
+system.cpu2: completed 50000 read accesses @28834360
+system.cpu7: completed 50000 read accesses @28946860
+system.cpu4: completed 60000 read accesses @34313400
+system.cpu5: completed 60000 read accesses @34314670
+system.cpu3: completed 60000 read accesses @34419440
+system.cpu1: completed 60000 read accesses @34450630
+system.cpu6: completed 60000 read accesses @34477780
+system.cpu0: completed 60000 read accesses @34500340
+system.cpu2: completed 60000 read accesses @34535810
+system.cpu7: completed 60000 read accesses @34657810
+system.cpu5: completed 70000 read accesses @40003670
+system.cpu4: completed 70000 read accesses @40058990
+system.cpu3: completed 70000 read accesses @40162430
+system.cpu0: completed 70000 read accesses @40197610
+system.cpu6: completed 70000 read accesses @40218844
+system.cpu1: completed 70000 read accesses @40223070
+system.cpu2: completed 70000 read accesses @40246640
+system.cpu7: completed 70000 read accesses @40416250
+system.cpu5: completed 80000 read accesses @45745700
+system.cpu4: completed 80000 read accesses @45764460
+system.cpu3: completed 80000 read accesses @45881080
+system.cpu0: completed 80000 read accesses @45887290
+system.cpu2: completed 80000 read accesses @45902430
+system.cpu6: completed 80000 read accesses @45914170
+system.cpu1: completed 80000 read accesses @46020320
+system.cpu7: completed 80000 read accesses @46126230
+system.cpu5: completed 90000 read accesses @51539850
+system.cpu6: completed 90000 read accesses @51572100
+system.cpu4: completed 90000 read accesses @51579370
+system.cpu0: completed 90000 read accesses @51603670
+system.cpu3: completed 90000 read accesses @51633670
+system.cpu2: completed 90000 read accesses @51656890
+system.cpu1: completed 90000 read accesses @51768690
+system.cpu7: completed 90000 read accesses @51933040
+system.cpu5: completed 100000 read accesses @57251340
 hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
index 5cb14d0de..1c1816479 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 20 2010 12:21:09
-M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
-M5 started Aug 20 2010 13:38:22
-M5 executing on SC2B0629
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:38
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 11059012 because maximum number of loads reached
+Exiting @ tick 57251340 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index 09849fe3c..4df469f73 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 341104                       # Number of bytes of host memory used
-host_seconds                                    68.57                       # Real time elapsed on the host
-host_tick_rate                                 161272                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 363908                       # Number of bytes of host memory used
+host_seconds                                   189.81                       # Real time elapsed on the host
+host_tick_rate                                 301617                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_seconds                                  0.011059                       # Number of seconds simulated
-sim_ticks                                    11059012                       # Number of ticks simulated
+sim_seconds                                  0.057251                       # Number of seconds simulated
+sim_ticks                                    57251340                       # Number of ticks simulated
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.num_reads                           99622                       # number of read accesses completed
-system.cpu0.num_writes                          53973                       # number of write accesses completed
+system.cpu0.num_reads                           99892                       # number of read accesses completed
+system.cpu0.num_writes                          53261                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99717                       # number of read accesses completed
-system.cpu1.num_writes                          53880                       # number of write accesses completed
+system.cpu1.num_reads                           99647                       # number of read accesses completed
+system.cpu1.num_writes                          53706                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           99983                       # number of read accesses completed
-system.cpu2.num_writes                          53618                       # number of write accesses completed
+system.cpu2.num_reads                           99764                       # number of read accesses completed
+system.cpu2.num_writes                          53616                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99512                       # number of read accesses completed
-system.cpu3.num_writes                          54081                       # number of write accesses completed
+system.cpu3.num_reads                           99684                       # number of read accesses completed
+system.cpu3.num_writes                          53704                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                          100000                       # number of read accesses completed
-system.cpu4.num_writes                          53593                       # number of write accesses completed
+system.cpu4.num_reads                           99856                       # number of read accesses completed
+system.cpu4.num_writes                          53900                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99946                       # number of read accesses completed
-system.cpu5.num_writes                          53647                       # number of write accesses completed
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          53611                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           99718                       # number of read accesses completed
-system.cpu6.num_writes                          53875                       # number of write accesses completed
+system.cpu6.num_reads                           99838                       # number of read accesses completed
+system.cpu6.num_writes                          54123                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           99976                       # number of read accesses completed
-system.cpu7.num_writes                          53616                       # number of write accesses completed
+system.cpu7.num_reads                           99183                       # number of read accesses completed
+system.cpu7.num_writes                          53528                       # number of write accesses completed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index 5a4805332..4e966d986 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
 mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu0]
 type=MemTest
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
index 073fadf83..f3966712d 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep 20 2010 15:04:49
-M5 revision 0c4a7d867247 7686 default qtip print-identical tip
-M5 started Sep 20 2010 15:50:04
-M5 executing on phenom
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:38
+M5 executing on burrito
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 263488655 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
index 54a425295..cebf442c3 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 318984                       # Number of bytes of host memory used
-host_seconds                                   150.28                       # Real time elapsed on the host
-host_tick_rate                                1753313                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 349812                       # Number of bytes of host memory used
+host_seconds                                   357.32                       # Real time elapsed on the host
+host_tick_rate                                 737410                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000263                       # Number of seconds simulated
 sim_ticks                                   263488655                       # Number of ticks simulated
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index 2e46bddba..247e64cce 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 physmem ruby
+children=dir_cntrl0 l1_cntrl0 physmem ruby tester
 mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -52,38 +61,16 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=sequencer
 buffer_size=0
-cacheMemory=system.l1_cntrl0.sequencer.icache
+cacheMemory=system.ruby.cpu_ruby_ports.dcache
 cache_response_latency=12
 issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.l1_cntrl0.sequencer
+sequencer=system.ruby.cpu_ruby_ports
 transitions_per_cycle=32
 version=0
 
-[system.l1_cntrl0.sequencer]
-type=RubySequencer
-children=icache
-dcache=system.l1_cntrl0.sequencer.icache
-deadlock_threshold=500000
-icache=system.l1_cntrl0.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=true
-version=0
-physMemPort=system.physmem.port[0]
-port=root.cpuPort[0]
-
-[system.l1_cntrl0.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
-
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -92,14 +79,13 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
 block_size_bytes=64
 clock=1
-debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -109,13 +95,27 @@ randomization=true
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+children=dcache
+access_phys_mem=true
+dcache=system.ruby.cpu_ruby_ports.dcache
+deadlock_threshold=500000
+icache=system.ruby.cpu_ruby_ports.dcache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=system.tester.cpuPort[0]
+
+[system.ruby.cpu_ruby_ports.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -131,9 +131,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
+description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
-name=Crossbar
 num_int_nodes=3
 print_config=false
 
@@ -179,3 +179,10 @@ num_of_sequencers=1
 type=RubyTracer
 warmup_length=100000
 
+[system.tester]
+type=RubyTester
+checks_to_complete=100
+deadlock_threshold=50000
+wakeup_frequency=10
+cpuPort=system.ruby.cpu_ruby_ports.port[0]
+
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
index 4b8c316dc..ce11e4002 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: Crossbar
+topology: 
 
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Aug/05/2010 10:10:57
+Real time: Feb/07/2011 01:47:37
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.29
-Virtual_time_in_minutes: 0.00483333
-Virtual_time_in_hours:   8.05556e-05
-Virtual_time_in_days:    3.35648e-06
+Virtual_time_in_seconds: 0.3
+Virtual_time_in_minutes: 0.005
+Virtual_time_in_hours:   8.33333e-05
+Virtual_time_in_days:    3.47222e-06
 
 Ruby_current_time: 281031
 Ruby_start_time: 0
 Ruby_cycles: 281031
 
-mbytes_resident: 30.9531
-mbytes_total: 203.703
-resident_ratio: 0.15199
+mbytes_resident: 34.3867
+mbytes_total: 225.355
+resident_ratio: 0.152606
 
 ruby_cycles_executed: [ 281032 ]
 
@@ -122,11 +122,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9003
+page_reclaims: 9878
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 48
 
 Network Stats
 -------------
@@ -170,18 +170,18 @@ links_utilized_percent_switch_2: 0.169999
   outgoing_messages_switch_2_link_1_Control: 957 7656 [ 0 0 957 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Data: 954 68688 [ 0 0 954 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.l1_cntrl0.sequencer.icache
-  system.l1_cntrl0.sequencer.icache_total_misses: 957
-  system.l1_cntrl0.sequencer.icache_total_demand_misses: 957
-  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
-  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
-  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+Cache Stats: system.ruby.cpu_ruby_ports.dcache
+  system.ruby.cpu_ruby_ports.dcache_total_misses: 957
+  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 957
+  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
+  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
+  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
 
-  system.l1_cntrl0.sequencer.icache_request_type_LD:   4.91118%
-  system.l1_cntrl0.sequencer.icache_request_type_ST:   89.7597%
-  system.l1_cntrl0.sequencer.icache_request_type_IFETCH:   5.32915%
+  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   4.91118%
+  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   89.7597%
+  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   5.32915%
 
-  system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode:   957    100%
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   957    100%
 
  --- L1Cache ---
  - Event Counts -
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index 566ba5c1a..e67c01bd9 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  4 2010 17:29:21
-M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
-M5 started Aug  5 2010 10:10:57
-M5 executing on SC2B0617
+M5 compiled Feb  7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:47:37
+M5 executing on burrito
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 104ae3de6..e1f5ad3f1 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 208596                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
-host_tick_rate                                3195386                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230768                       # Number of bytes of host memory used
+host_seconds                                     0.30                       # Real time elapsed on the host
+host_tick_rate                                 934733                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000281                       # Number of seconds simulated
 sim_ticks                                      281031                       # Number of ticks simulated
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 84f87c01b..540e1709f 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -3,17 +3,24 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami
 boot_cpu_frequency=1
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=drivesys.physmem
-readfile=/arm/scratch/alisai01/m5/configs/boot/netperf-server.rcS
+readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [drivesys.bridge]
 type=Bridge
@@ -91,7 +98,7 @@ table_size=65536
 
 [drivesys.disk0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [drivesys.disk2]
@@ -111,7 +118,7 @@ table_size=65536
 
 [drivesys.disk2.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [drivesys.intrctrl]
@@ -175,7 +182,7 @@ system=drivesys
 
 [drivesys.simple_disk.disk]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [drivesys.terminal]
@@ -637,7 +644,9 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
+ctrl_offset=0
 disks=drivesys.disk0 drivesys.disk2
+io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
@@ -706,24 +715,33 @@ int1=drivesys.tsunami.ethernet.interface
 [root]
 type=Root
 children=drivesys etherdump etherlink testsys
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [testsys]
 type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami
 boot_cpu_frequency=1
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=testsys.physmem
-readfile=/arm/scratch/alisai01/m5/configs/boot/netperf-stream-client.rcS
+readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [testsys.bridge]
 type=Bridge
@@ -801,7 +819,7 @@ table_size=65536
 
 [testsys.disk0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [testsys.disk2]
@@ -821,7 +839,7 @@ table_size=65536
 
 [testsys.disk2.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [testsys.intrctrl]
@@ -885,7 +903,7 @@ system=testsys
 
 [testsys.simple_disk.disk]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [testsys.terminal]
@@ -1347,7 +1365,9 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
+ctrl_offset=0
 disks=testsys.disk0 testsys.disk2
+io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
index c18ca3505..d5294a000 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
@@ -2,6 +2,10 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: Obsolete M5 ivlb instruction encountered.
 For more information see: http://www.m5sim.org/warn/fcbd217d
 hack: be nice to actually delete the event here
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index 2dcdfae87..62b569073 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 23:00:12
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 23:11:17
-M5 executing on aus-bc2-b15
+M5 compiled Feb  7 2011 01:46:17
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:46:32
+M5 executing on burrito
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 4300236804024 because checkpoint
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 9fb1ef54c..a776ca423 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -93,8 +93,24 @@ drivesys.cpu.kern.syscall::150                      1      4.55%    100.00% # nu
 drivesys.cpu.kern.syscall::total                   22                       # number of syscalls executed
 drivesys.cpu.not_idle_fraction               0.000010                       # Percentage of non-idle cycles
 drivesys.cpu.numCycles                   199571362884                       # number of cpu cycles simulated
+drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
+drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
+drivesys.cpu.num_busy_cycles             1954747.881971                       # Number of busy cycles
+drivesys.cpu.num_conditional_control_insts       161093                       # number of instructions that are conditional controls
+drivesys.cpu.num_fp_alu_accesses                 1278                       # Number of float alu accesses
+drivesys.cpu.num_fp_insts                        1278                       # number of float instructions
+drivesys.cpu.num_fp_register_reads                694                       # number of times the floating registers were read
+drivesys.cpu.num_fp_register_writes               698                       # number of times the floating registers were written
+drivesys.cpu.num_func_calls                    121650                       # number of times a function call or return occured
+drivesys.cpu.num_idle_cycles             199569408136.118042                       # Number of idle cycles
 drivesys.cpu.num_insts                        1958129                       # Number of instructions executed
-drivesys.cpu.num_refs                          625939                       # Number of memory references
+drivesys.cpu.num_int_alu_accesses             1889973                       # Number of integer alu accesses
+drivesys.cpu.num_int_insts                    1889973                       # number of integer instructions
+drivesys.cpu.num_int_register_reads           2411030                       # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes          1442447                       # number of times the integer registers were written
+drivesys.cpu.num_load_insts                    394697                       # Number of load instructions
+drivesys.cpu.num_mem_refs                      625939                       # number of memory refs
+drivesys.cpu.num_store_insts                   231242                       # Number of store instructions
 drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
 drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
 drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
@@ -156,10 +172,10 @@ drivesys.tsunami.ethernet.txPPS                    25                       # Pa
 drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
 drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
 drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-host_inst_rate                              245765975                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 512700                       # Number of bytes of host memory used
-host_seconds                                     1.11                       # Real time elapsed on the host
-host_tick_rate                           179775828937                       # Simulator tick rate (ticks/s)
+host_inst_rate                               71982907                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 498216                       # Number of bytes of host memory used
+host_seconds                                     3.80                       # Real time elapsed on the host
+host_tick_rate                            52659325700                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.200001                       # Number of seconds simulated
@@ -267,8 +283,24 @@ testsys.cpu.kern.syscall::118                       2      2.41%    100.00% # nu
 testsys.cpu.kern.syscall::total                    83                       # number of syscalls executed
 testsys.cpu.not_idle_fraction                0.000018                       # Percentage of non-idle cycles
 testsys.cpu.numCycles                    199569460393                       # number of cpu cycles simulated
+testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
+testsys.cpu.num_busy_cycles              3558262.534294                       # Number of busy cycles
+testsys.cpu.num_conditional_control_insts       361828                       # number of instructions that are conditional controls
+testsys.cpu.num_fp_alu_accesses                 17380                       # Number of float alu accesses
+testsys.cpu.num_fp_insts                        17380                       # number of float instructions
+testsys.cpu.num_fp_register_reads               11166                       # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes              10823                       # number of times the floating registers were written
+testsys.cpu.num_func_calls                     107994                       # number of times a function call or return occured
+testsys.cpu.num_idle_cycles              199565902130.465698                       # Number of idle cycles
 testsys.cpu.num_insts                         3560411                       # Number of instructions executed
-testsys.cpu.num_refs                          1173234                       # Number of memory references
+testsys.cpu.num_int_alu_accesses              3348322                       # Number of integer alu accesses
+testsys.cpu.num_int_insts                     3348322                       # number of integer instructions
+testsys.cpu.num_int_register_reads            4592571                       # number of times the integer registers were read
+testsys.cpu.num_int_register_writes           2442795                       # number of times the integer registers were written
+testsys.cpu.num_load_insts                     666253                       # Number of load instructions
+testsys.cpu.num_mem_refs                      1173234                       # number of memory refs
+testsys.cpu.num_store_insts                    506981                       # Number of store instructions
 testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
 testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
 testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
@@ -386,8 +418,24 @@ drivesys.cpu.kern.mode_ticks::idle                  0                       # nu
 drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
 drivesys.cpu.not_idle_fraction                      0                       # Percentage of non-idle cycles
 drivesys.cpu.numCycles                              0                       # number of cpu cycles simulated
+drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
+drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
+drivesys.cpu.num_busy_cycles                        0                       # Number of busy cycles
+drivesys.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+drivesys.cpu.num_fp_alu_accesses                    0                       # Number of float alu accesses
+drivesys.cpu.num_fp_insts                           0                       # number of float instructions
+drivesys.cpu.num_fp_register_reads                  0                       # number of times the floating registers were read
+drivesys.cpu.num_fp_register_writes                 0                       # number of times the floating registers were written
+drivesys.cpu.num_func_calls                         0                       # number of times a function call or return occured
+drivesys.cpu.num_idle_cycles                        0                       # Number of idle cycles
 drivesys.cpu.num_insts                              0                       # Number of instructions executed
-drivesys.cpu.num_refs                               0                       # Number of memory references
+drivesys.cpu.num_int_alu_accesses                   0                       # Number of integer alu accesses
+drivesys.cpu.num_int_insts                          0                       # number of integer instructions
+drivesys.cpu.num_int_register_reads                 0                       # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes                0                       # number of times the integer registers were written
+drivesys.cpu.num_load_insts                         0                       # Number of load instructions
+drivesys.cpu.num_mem_refs                           0                       # number of memory refs
+drivesys.cpu.num_store_insts                        0                       # Number of store instructions
 drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
 drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
 drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
@@ -431,10 +479,10 @@ drivesys.tsunami.ethernet.totalSwi                  0                       # to
 drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
 drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
 drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-host_inst_rate                           151538155765                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 512700                       # Number of bytes of host memory used
+host_inst_rate                            86035621838                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 498216                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              415641460                       # Simulator tick rate (ticks/s)
+host_tick_rate                              235143018                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
@@ -491,8 +539,24 @@ testsys.cpu.kern.mode_ticks::idle                   0                       # nu
 testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
 testsys.cpu.not_idle_fraction                       0                       # Percentage of non-idle cycles
 testsys.cpu.numCycles                               0                       # number of cpu cycles simulated
+testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
+testsys.cpu.num_busy_cycles                         0                       # Number of busy cycles
+testsys.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+testsys.cpu.num_fp_alu_accesses                     0                       # Number of float alu accesses
+testsys.cpu.num_fp_insts                            0                       # number of float instructions
+testsys.cpu.num_fp_register_reads                   0                       # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes                  0                       # number of times the floating registers were written
+testsys.cpu.num_func_calls                          0                       # number of times a function call or return occured
+testsys.cpu.num_idle_cycles                         0                       # Number of idle cycles
 testsys.cpu.num_insts                               0                       # Number of instructions executed
-testsys.cpu.num_refs                                0                       # Number of memory references
+testsys.cpu.num_int_alu_accesses                    0                       # Number of integer alu accesses
+testsys.cpu.num_int_insts                           0                       # number of integer instructions
+testsys.cpu.num_int_register_reads                  0                       # number of times the integer registers were read
+testsys.cpu.num_int_register_writes                 0                       # number of times the integer registers were written
+testsys.cpu.num_load_insts                          0                       # Number of load instructions
+testsys.cpu.num_mem_refs                            0                       # number of memory refs
+testsys.cpu.num_store_insts                         0                       # Number of store instructions
 testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
 testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
 testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-- 
2.30.2