From 0858b8bf6c7dd8c9d7fc3f4841bb182f4cee6b2a Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 24 Sep 2019 12:30:02 +0000 Subject: [PATCH] lib.cdc: specify maximum input delay in seconds. Since we use hertz elsewhere, this provides for easy conversions. Also, cast the delay to string before applying it in xilinx_7series, to avoid stripping the fractional digits. Closes #234. --- nmigen/lib/cdc.py | 4 ++-- nmigen/vendor/xilinx_7series.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py index 452814d..9e0ad72 100644 --- a/nmigen/lib/cdc.py +++ b/nmigen/lib/cdc.py @@ -39,7 +39,7 @@ class FFSynchronizer(Elaboratable): Number of synchronization stages between input and output. The lowest safe number is 2, with higher numbers reducing MTBF further, at the cost of increased latency. max_input_delay : None or float - Maximum delay from the input signal's clock to the first synchronization stage. + Maximum delay from the input signal's clock to the first synchronization stage, in seconds. If specified and the platform does not support it, elaboration will fail. Platform override @@ -122,7 +122,7 @@ class ResetSynchronizer(Elaboratable): Number of synchronization stages between input and output. The lowest safe number is 2, with higher numbers reducing MTBF further, at the cost of increased deassertion latency. max_input_delay : None or float - Maximum delay from the input signal's clock to the first synchronization stage. + Maximum delay from the input signal's clock to the first synchronization stage, in seconds. If specified and the platform does not support it, elaboration will fail. Platform override diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index da7fd2b..ca42054 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -392,7 +392,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): if ff_sync._max_input_delay is None: flops[0].attrs["nmigen.vivado.false_path"] = "TRUE" else: - flops[0].attrs["nmigen.vivado.max_delay"] = ff_sync._max_input_delay + flops[0].attrs["nmigen.vivado.max_delay"] = str(ff_sync._max_input_delay * 1e9) for i, o in zip((ff_sync.i, *flops), flops): m.d[ff_sync._o_domain] += o.eq(i) m.d.comb += ff_sync.o.eq(flops[-1]) @@ -407,7 +407,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): if reset_sync._max_input_delay is None: flops[0].attrs["nmigen.vivado.false_path"] = "TRUE" else: - flops[0].attrs["nmigen.vivado.max_delay"] = reset_sync._max_input_delay + flops[0].attrs["nmigen.vivado.max_delay"] = str(reset_sync._max_input_delay * 1e9) for i, o in zip((0, *flops), flops): m.d.reset_sync += o.eq(i) m.d.comb += [ -- 2.30.2