From 0873141305d972a0811b2273e463cecf919d84c9 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Tue, 16 Jun 2020 16:23:55 +0200 Subject: [PATCH] Update switch to nMigen syntax --- gram/phy/ecp5ddrphy.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index ad4b7c9..9a3818d 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -264,11 +264,11 @@ class ECP5DDRPHY(Peripheral, Elaboratable): m.d.sync += dqs_bitslip.eq(0) with m.Elif(self._rdly_dq_bitslip.w_stb): m.d.sync += dqs_bitslip.eq(dqs_bitslip + 1) - dqs_cases = {} - for j, b in enumerate(range(-2, 2)): - dqs_cases[j] = dqs_read.eq( - rddata_en[cl_sys_latency + b:cl_sys_latency + b + 2] != 0) - m.d.sync += Case(dqs_bitslip, dqs_cases) + with m.Switch(dqs_bitslip): + for j, b in enumerate(range(-2, 2)): + with m.Case(j): + m.d.sync += dqs_read.eq(rddata_en[cl_sys_latency + b:cl_sys_latency + b + 2] != 0) + m.submodules += Instance("DQSBUFM", p_DQS_LI_DEL_ADJ="MINUS", p_DQS_LI_DEL_VAL=1, -- 2.30.2