From 087b7f0d2302abf9e82a32253b395f1c60237420 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 6 Jul 2022 14:22:54 +0100 Subject: [PATCH] update pinmux submodule, rename to "fabric" --- pinmux | 2 +- src/soc/config/pinouts.py | 2 +- src/soc/debug/.gitignore | 1 + src/soc/simple/issuer.py | 6 +++--- 4 files changed, 6 insertions(+), 5 deletions(-) create mode 100644 src/soc/debug/.gitignore diff --git a/pinmux b/pinmux index d96f737c..7cbf0e2a 160000 --- a/pinmux +++ b/pinmux @@ -1 +1 @@ -Subproject commit d96f737c0a53dde983060522816bbef016b449ce +Subproject commit 7cbf0e2a54448f549243cd602ebafd10de8d32f0 diff --git a/src/soc/config/pinouts.py b/src/soc/config/pinouts.py index 95129b19..9ebe4f7c 100644 --- a/src/soc/config/pinouts.py +++ b/src/soc/config/pinouts.py @@ -98,7 +98,7 @@ def load_pinouts(chipname=None): # path is relative to this filename, in the pinmux submodule pinmux = os.getenv("PINMUX", "%s/../../../pinmux" % pth) - fname = "%s/%s/litex_pinpads.json" % (pinmux, chipname) + fname = "%s/%s/fabric_pinpads.json" % (pinmux, chipname) with open(fname) as f: txt = f.read() diff --git a/src/soc/debug/.gitignore b/src/soc/debug/.gitignore new file mode 100644 index 00000000..8edaee03 --- /dev/null +++ b/src/soc/debug/.gitignore @@ -0,0 +1 @@ +ls180_pins.py diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index cc372386..15bd1760 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -209,7 +209,7 @@ class TestIssuerBase(Elaboratable): #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock if self.jtag_en: - # XXX MUST keep this up-to-date with litex, and + # XXX MUST keep this up-to-date with fabric, and # soc-cocotb-sim, and err.. all needs sorting out, argh subset = ['uart', 'mtwi', @@ -415,7 +415,7 @@ class TestIssuerBase(Elaboratable): cur_state = self.cur_state - # 4x 4k SRAM blocks. these simply "exist", they get routed in litex + # 4x 4k SRAM blocks. these simply "exist", they get routed in fabric if self.sram4x4k: for i, sram in enumerate(self.sram4k): m.submodules["sram4k_%d" % i] = csd(sram) @@ -435,7 +435,7 @@ class TestIssuerBase(Elaboratable): m.submodules.simple_gpio = simple_gpio = csd(self.simple_gpio) # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl) - # XXX causes litex ECP5 test to get wrong idea about input and output + # XXX causes fabric ECP5 test to get wrong idea about input and output # (but works with verilator sim *sigh*) # if self.gpio and self.xics: # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0]) -- 2.30.2