From 087b80de6eb85d50f0e936709c804647d7084770 Mon Sep 17 00:00:00 2001 From: Joseph Myers Date: Thu, 29 Jan 2009 11:48:34 +0000 Subject: [PATCH] gas: 2009-01-29 Mark Mitchell * config/tc-arm.c (insns): Correct encoding of qadd, qdadd, qsub, qdsub in Thumb-2 mode. gas/testsuite: 2009-01-29 Mark Mitchell * gas/arm/thumb32.s (qadd): Add qadd, qdadd, qsub, and qdsub. * gas/arm/thumb32.d: Likewise. opcodes: 2009-01-29 Mark Mitchell * arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd, qsub, and qdsub. --- gas/ChangeLog | 5 ++++ gas/config/tc-arm.c | 8 +++--- gas/testsuite/ChangeLog | 5 ++++ gas/testsuite/gas/arm/thumb32.d | 44 ++++++++++++++++++--------------- gas/testsuite/gas/arm/thumb32.s | 4 +++ opcodes/ChangeLog | 5 ++++ opcodes/arm-dis.c | 8 +++--- 7 files changed, 51 insertions(+), 28 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 4cf790177ec..cc855cd137e 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2009-01-29 Mark Mitchell + + * config/tc-arm.c (insns): Correct encoding of qadd, qdadd, qsub, + qdsub in Thumb-2 mode. + 2009-01-29 Paul Brook Mark Mitchell diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index f7bca73c64b..0d4d005da24 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -15232,10 +15232,10 @@ static const struct asm_opcode insns[] = TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), - TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), - TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), - TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), - TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), + TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), + TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), + TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), + TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), #undef ARM_VARIANT #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 034ce59aedc..7bc3d8e2329 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2009-01-29 Mark Mitchell + + * gas/arm/thumb32.s (qadd): Add qadd, qdadd, qsub, and qdsub. + * gas/arm/thumb32.d: Likewise. + 2009-01-29 Paul Brook Mark Mitchell diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d index 1930e8954f4..406100ce3ba 100644 --- a/gas/testsuite/gas/arm/thumb32.d +++ b/gas/testsuite/gas/arm/thumb32.d @@ -682,9 +682,13 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> bd02 pop \{r1, pc\} 0[0-9a-f]+ <[^>]+> e92d 1f00 stmdb sp!, \{r8, r9, sl, fp, ip\} 0[0-9a-f]+ <[^>]+> e8bd 1f00 ldmia\.w sp!, \{r8, r9, sl, fp, ip\} +0[0-9a-f]+ <[^>]+> fa82 f183 qadd r1, r2, r3 0[0-9a-f]+ <[^>]+> fa92 f113 qadd16 r1, r2, r3 0[0-9a-f]+ <[^>]+> fa82 f113 qadd8 r1, r2, r3 0[0-9a-f]+ <[^>]+> faa2 f113 qaddsubx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f193 qdadd r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f1b3 qdsub r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f1a3 qsub r1, r2, r3 0[0-9a-f]+ <[^>]+> fad2 f113 qsub16 r1, r2, r3 0[0-9a-f]+ <[^>]+> fac2 f113 qsub8 r1, r2, r3 0[0-9a-f]+ <[^>]+> fae2 f113 qsubaddx r1, r2, r3 @@ -913,26 +917,26 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> fa52 f183 uxtab r1, r2, r3 0[0-9a-f]+ <[^>]+> fa32 f183 uxtab16 r1, r2, r3 0[0-9a-f]+ <[^>]+> fa12 f183 uxtah r1, r2, r3 -0[0-9a-f]+ <[^>]+> f89f 12aa ldrb\.w r1, \[pc, #682\] ; 0+e02 <[^>]+> -0[0-9a-f]+ <[^>]+> f89f 1155 ldrb\.w r1, \[pc, #341\] ; 0+cb1 <[^>]+> -0[0-9a-f]+ <[^>]+> f81f 12aa ldrb\.w r1, \[pc, #-682\] ; 0+8b6 <[^>]+> -0[0-9a-f]+ <[^>]+> f81f 1155 ldrb\.w r1, \[pc, #-341\] ; 0+a0f <[^>]+> -0[0-9a-f]+ <[^>]+> f99f 12aa ldrsb\.w r1, \[pc, #682\] ; 0+e12 <[^>]+> -0[0-9a-f]+ <[^>]+> f99f 1155 ldrsb\.w r1, \[pc, #341\] ; 0+cc1 <[^>]+> -0[0-9a-f]+ <[^>]+> f91f 12aa ldrsb\.w r1, \[pc, #-682\] ; 0+8c6 <[^>]+> -0[0-9a-f]+ <[^>]+> f91f 1155 ldrsb\.w r1, \[pc, #-341\] ; 0+a1f <[^>]+> -0[0-9a-f]+ <[^>]+> f8bf 12aa ldrh\.w r1, \[pc, #682\] ; 0+e22 <[^>]+> -0[0-9a-f]+ <[^>]+> f8bf 1155 ldrh\.w r1, \[pc, #341\] ; 0+cd1 <[^>]+> -0[0-9a-f]+ <[^>]+> f83f 12aa ldrh\.w r1, \[pc, #-682\] ; 0+8d6 <[^>]+> -0[0-9a-f]+ <[^>]+> f83f 1155 ldrh\.w r1, \[pc, #-341\] ; 0+a2f <[^>]+> -0[0-9a-f]+ <[^>]+> f9bf 12aa ldrsh\.w r1, \[pc, #682\] ; 0+e32 <[^>]+> -0[0-9a-f]+ <[^>]+> f9bf 1155 ldrsh\.w r1, \[pc, #341\] ; 0+ce1 <[^>]+> -0[0-9a-f]+ <[^>]+> f93f 12aa ldrsh\.w r1, \[pc, #-682\] ; 0+8e6 <[^>]+> -0[0-9a-f]+ <[^>]+> f93f 1155 ldrsh\.w r1, \[pc, #-341\] ; 0+a3f <[^>]+> -0[0-9a-f]+ <[^>]+> f8df 12aa ldr\.w r1, \[pc, #682\] ; 0+e42 <[^>]+> -0[0-9a-f]+ <[^>]+> f8df 1155 ldr\.w r1, \[pc, #341\] ; 0+cf1 <[^>]+> -0[0-9a-f]+ <[^>]+> f85f 12aa ldr\.w r1, \[pc, #-682\] ; 0+8f6 <[^>]+> -0[0-9a-f]+ <[^>]+> f85f 1155 ldr\.w r1, \[pc, #-341\] ; 0+a4f <[^>]+> +0[0-9a-f]+ <[^>]+> f89f 12aa ldrb\.w r1, \[pc, #682\] ; 0+e12 <[^>]+> +0[0-9a-f]+ <[^>]+> f89f 1155 ldrb\.w r1, \[pc, #341\] ; 0+cc1 <[^>]+> +0[0-9a-f]+ <[^>]+> f81f 12aa ldrb\.w r1, \[pc, #-682\] ; 0+8c6 <[^>]+> +0[0-9a-f]+ <[^>]+> f81f 1155 ldrb\.w r1, \[pc, #-341\] ; 0+a1f <[^>]+> +0[0-9a-f]+ <[^>]+> f99f 12aa ldrsb\.w r1, \[pc, #682\] ; 0+e22 <[^>]+> +0[0-9a-f]+ <[^>]+> f99f 1155 ldrsb\.w r1, \[pc, #341\] ; 0+cd1 <[^>]+> +0[0-9a-f]+ <[^>]+> f91f 12aa ldrsb\.w r1, \[pc, #-682\] ; 0+8d6 <[^>]+> +0[0-9a-f]+ <[^>]+> f91f 1155 ldrsb\.w r1, \[pc, #-341\] ; 0+a2f <[^>]+> +0[0-9a-f]+ <[^>]+> f8bf 12aa ldrh\.w r1, \[pc, #682\] ; 0+e32 <[^>]+> +0[0-9a-f]+ <[^>]+> f8bf 1155 ldrh\.w r1, \[pc, #341\] ; 0+ce1 <[^>]+> +0[0-9a-f]+ <[^>]+> f83f 12aa ldrh\.w r1, \[pc, #-682\] ; 0+8e6 <[^>]+> +0[0-9a-f]+ <[^>]+> f83f 1155 ldrh\.w r1, \[pc, #-341\] ; 0+a3f <[^>]+> +0[0-9a-f]+ <[^>]+> f9bf 12aa ldrsh\.w r1, \[pc, #682\] ; 0+e42 <[^>]+> +0[0-9a-f]+ <[^>]+> f9bf 1155 ldrsh\.w r1, \[pc, #341\] ; 0+cf1 <[^>]+> +0[0-9a-f]+ <[^>]+> f93f 12aa ldrsh\.w r1, \[pc, #-682\] ; 0+8f6 <[^>]+> +0[0-9a-f]+ <[^>]+> f93f 1155 ldrsh\.w r1, \[pc, #-341\] ; 0+a4f <[^>]+> +0[0-9a-f]+ <[^>]+> f8df 12aa ldr\.w r1, \[pc, #682\] ; 0+e52 <[^>]+> +0[0-9a-f]+ <[^>]+> f8df 1155 ldr\.w r1, \[pc, #341\] ; 0+d01 <[^>]+> +0[0-9a-f]+ <[^>]+> f85f 12aa ldr\.w r1, \[pc, #-682\] ; 0+906 <[^>]+> +0[0-9a-f]+ <[^>]+> f85f 1155 ldr\.w r1, \[pc, #-341\] ; 0+a5f <[^>]+> 0[0-9a-f]+ <[^>]+> f200 0900 addw r9, r0, #0 ; 0x0 0[0-9a-f]+ <[^>]+> f60f 76ff addw r6, pc, #4095 ; 0xfff 0[0-9a-f]+ <[^>]+> f6a9 2685 subw r6, r9, #2693 ; 0xa85 diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s index 697dfd240f3..a4653d083d8 100644 --- a/gas/testsuite/gas/arm/thumb32.s +++ b/gas/testsuite/gas/arm/thumb32.s @@ -526,9 +526,13 @@ push_pop: pop {r8,r9,r10,r11,r12} qadd: + qadd r1, r2, r3 qadd16 r1, r2, r3 qadd8 r1, r2, r3 qaddsubx r1, r2, r3 + qdadd r1, r2, r3 + qdsub r1, r2, r3 + qsub r1, r2, r3 qsub16 r1, r2, r3 qsub8 r1, r2, r3 qsubaddx r1, r2, r3 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 402cece6510..7466da19ab1 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2009-01-29 Mark Mitchell + + * arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd, + qsub, and qdsub. + 2009-01-28 Chao-ying Fu * mips-opc.c (suxc1): Add the flag of FP_D. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index f462143eb35..44c2383cab3 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1280,10 +1280,10 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, -- 2.30.2