From 0883e99de3aad61fa98a73a5e61d9785ee5668e2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Jul 2013 19:25:29 +0200 Subject: [PATCH] Do not specify period constraints twice --- mibuild/platforms/m1.py | 2 +- mibuild/platforms/mixxeo.py | 2 +- mibuild/xilinx_ise.py | 7 ++++--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index 80d61a14..a096a38a 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -119,7 +119,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, - lambda p: CRG_SE(p, "clk50", "user_btn", 20.0)) + lambda p: CRG_SE(p, "clk50", "user_btn")) def do_finalize(self, fragment): try: diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index ebf87c3c..4ea76460 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -143,7 +143,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-3", _io, - lambda p: CRG_SE(p, "clk50", None, 20.0)) + lambda p: CRG_SE(p, "clk50", None)) self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n") def do_finalize(self, fragment): diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 2bc8c107..2ff3abec 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -10,16 +10,17 @@ from mibuild.crg import SimpleCRG from mibuild import tools def _add_period_constraint(platform, clk, period): - platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk"; + if period is not None: + platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk"; TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk) class CRG_SE(SimpleCRG): - def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): + def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) _add_period_constraint(platform, self._clk, period) class CRG_DS(Module): - def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): + def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False): reset_less = rst_name is None self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less) self._clk = platform.request(clk_name) -- 2.30.2