From 08a4ab72c2f7af84acea715b06285b0496c4a416 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 10 May 2021 16:10:14 +0100 Subject: [PATCH] add catch of MemException in ISACaller to raise unaligned exception 0x600 DAR is set as the address raised from the exception --- src/openpower/decoder/isa/caller.py | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index a30fd4cc..0d9c00ca 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -33,7 +33,7 @@ from openpower.consts import SVP64CROffs from openpower.decoder.power_svp64 import SVP64RM, decode_extra from openpower.decoder.isa.radixmmu import RADIX -from openpower.decoder.isa.mem import Mem, swap_order +from openpower.decoder.isa.mem import Mem, swap_order, MemException from collections import namedtuple import math @@ -782,7 +782,18 @@ class ISACaller: code = self.disassembly[self._pc] print("sim-execute", hex(self._pc), code) opname = code.split(' ')[0] - yield from self.call(opname) + try: + yield from self.call(opname) # execute the instruction + except MemException as e: # check for memory errors + if e.args[0] != 'unaligned': # only doing aligned at the mo + raise e # ... re-raise + # run a Trap but set DAR first + print ("memory unaligned exception, DAR", e.dar) + self.spr['DAR'] = e.dar + self.TRAP(0x600, PIb.PRIV) + self.namespace['NIA'] = self.trap_nia + self.pc.update(self.namespace, self.is_svp64_mode) + return # don't use this except in special circumstances if not self.respect_pc: -- 2.30.2