From 08ab36cabc11ebadf24d0f74c4a1aeac2d1101a0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 16:15:07 +0100 Subject: [PATCH] add category descriptions --- simple_v_extension/opcodes.mdwn | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn index c823fb9a0..836d5fd5b 100644 --- a/simple_v_extension/opcodes.mdwn +++ b/simple_v_extension/opcodes.mdwn @@ -2,18 +2,21 @@ Based on information from Michael Clark's riscv-meta opcodes table, this page categorises and identifies the type of parallelism that SimpleV -indirectly adds on each RISC-V **standard** opcode. +indirectly adds on each RISC-V **standard** opcode. These are note-form: +see [[specification]] for full details. * **-** no change of behaviour takes place: operation remains - **completely scalar** even if it has registers. + **completely scalar** as an **unmodified**, unaugmented standard RISC-V + opcode, even if it has registers. * **sv** - a standard contiguous (optionally predicated, optionally - indirected) multi-register operation where the predication for - the operation is taken from the **destination** register + indirected) multi-register operation where the predication register + to be used for the sequence of contiguous operations is taken from the + **destination** register's predication lookup entry. * **2v** - a standard contiguous (optionally twin-predicated, optionally indirected) twin-register operation (distinct source and destination) where either or both of source or destination may be redirected, vectorised, or **independently** predicated. This behaviour - covers the **entire** VMV, VSPLAT, VINSERT, VREDUCE, VSCATTER, VGATHER + covers the *entire* MV, VSPLAT, VINSERT, VREDUCE, VSCATTER, VGATHER paradigm. * **vld** - a standard contiguous (optionally twin-predicated, optionally indirected) multi-register load operation where either or both of @@ -26,7 +29,7 @@ indirectly adds on each RISC-V **standard** opcode. that is incremented (by the element width of the **source** register) * **VSU** - a similarly "Unit Stride" variant of **vst**. * **VBR** - a standard branch operation (optionally predicated, optionally - indirected) multi-register option where the (optional) predication for the + indirected) multi-register operation where the (optional) predication for the compare is taken from the destination register, and where (optionally) if the results of the multi-comparison are to be recorded, the **source** register's predication target is used. On completion of all compares, -- 2.30.2