From 08bf82a83cc3c6d1a0ea33d4a12fbbac98344c41 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 8 Oct 2018 18:12:15 +0100 Subject: [PATCH] add exceptions section --- simple_v_extension/specification.mdwn | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 2f4fe2e62..b9d0ec40a 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -759,6 +759,23 @@ during the hardware loop, **not** the offset. # Exceptions +TODO: expand. Exceptions may occur at any time, in any given underlying +scalar operation. This implies that context-switching (traps) may +occur, and operation must be returned to where it left off. That in +turn implies that the full state - including the current parallel +element being processed - has to be saved and restored. This is +what the **STATE** CSR is for. + +The implications are that all underlying individual scalar operations +"issued" by the parallelisation have to appear to be executed sequentially. +The further implications are that if two or more individual element +operations are underway, and one with an earlier index causes an exception, +it may be necessary for the microarchitecture to **discard** or terminate +operations with higher indices. + +This being somewhat dissatisfactory, an "opaque predication" variant +of the STATE CSR is being considered. + > And what about instructions like JALR?  answer: they're not vectorised, so not a problem -- 2.30.2