From 08d90fe8a5e12d92994c05b2ec9f68ab7232275c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 15 Jan 2009 16:50:58 +1000 Subject: [PATCH] r300: move some more function to generic --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 2 +- src/mesa/drivers/dri/r300/r300_context.h | 46 +--- src/mesa/drivers/dri/r300/r300_emit.c | 2 +- src/mesa/drivers/dri/r300/r300_emit.h | 95 ++++---- src/mesa/drivers/dri/r300/r300_ioctl.c | 4 +- src/mesa/drivers/dri/r300/r300_render.c | 220 +++++++++---------- src/mesa/drivers/dri/r300/r300_swtcl.c | 4 +- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 14 +- src/mesa/drivers/dri/radeon/common_context.h | 45 ++++ 9 files changed, 217 insertions(+), 215 deletions(-) diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index f4b4848cee2..30314d454ff 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -327,7 +327,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); struct radeon_renderbuffer *rrb; uint32_t zbpitch; diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 1a430169f5f..8449d00d37a 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -75,50 +75,7 @@ typedef struct r300_context *r300ContextPtr; #include "r300_vertprog.h" #include "r500_fragprog.h" -/** - * This function takes a float and packs it into a uint32_t - */ -static INLINE uint32_t r300PackFloat32(float fl) -{ - union { - float fl; - uint32_t u; - } u; - - u.fl = fl; - return u.u; -} - -/* This is probably wrong for some values, I need to test this - * some more. Range checking would be a good idea also.. - * - * But it works for most things. I'll fix it later if someone - * else with a better clue doesn't - */ -static INLINE uint32_t r300PackFloat24(float f) -{ - float mantissa; - int exponent; - uint32_t float24 = 0; - - if (f == 0.0) - return 0; - - mantissa = frexpf(f, &exponent); - /* Handle -ve */ - if (mantissa < 0) { - float24 |= (1 << 23); - mantissa = mantissa * -1.0; - } - /* Handle exponent, bias of 63 */ - exponent += 62; - float24 |= (exponent << 16); - /* Kill 7 LSB of mantissa */ - float24 |= (r300PackFloat32(mantissa) & 0x7FFFFF) >> 7; - - return float24; -} /************ DMA BUFFERS **************/ @@ -869,4 +826,7 @@ extern int r300VertexProgUpdateParams(GLcontext * ctx, #define RADEON_D_PLAYBACK_RAW 2 #define RADEON_D_T 3 +#define r300PackFloat32 radeonPackFloat32 +#define r300PackFloat24 radeonPackFloat24 + #endif /* __R300_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index a984f552bdf..bf33c18979d 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -493,7 +493,7 @@ void r300ReleaseArrays(GLcontext * ctx) void r300EmitCacheFlush(r300ContextPtr rmesa) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); BEGIN_BATCH(4); OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index db43cc3beed..1e7a639c000 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -138,28 +138,13 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) return cmd.u; } - -/** Single register write to command buffer; requires 2 dwords. */ -#define OUT_BATCH_REGVAL(reg, val) \ - OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), 1)); \ - OUT_BATCH((val)) - -/** Continuous register range write to command buffer; requires 1 dword, - * expects count dwords afterwards for register contents. */ -#define OUT_BATCH_REGSEQ(reg, count) \ - OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), (count))); - -/** Write a 32 bit float to the ring; requires 1 dword. */ -#define OUT_BATCH_FLOAT32(f) \ - OUT_BATCH(r300PackFloat32((f))); - /** * Write the header of a packet3 to the command buffer. * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. */ #define OUT_BATCH_PACKET3(packet, num_extra) do {\ - if (!b_l_r300->radeon.radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3(b_l_r300->radeon.radeonScreen,\ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\ R300_CMD_PACKET3_RAW)); \ }\ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ @@ -170,7 +155,7 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) */ void static INLINE end_3d(r300ContextPtr rmesa) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH(1); @@ -181,7 +166,7 @@ void static INLINE end_3d(r300ContextPtr rmesa) void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH(1); @@ -192,42 +177,42 @@ void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags) { - BATCH_LOCALS(rmesa); - uint32_t wait_until; - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags)); - END_BATCH(); - } else { - switch(flags) { - case R300_WAIT_2D: - wait_until = (1 << 14); - break; - case R300_WAIT_3D: - wait_until = (1 << 15); - break; - case R300_NEW_WAIT_2D_3D: - wait_until = (1 << 14) | (1 << 15); - break; - case R300_NEW_WAIT_2D_2D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - break; - case R300_NEW_WAIT_3D_3D_CLEAN: - wait_until = (1 << 15) | (1 << 17) | (1 << 18); - break; - case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - wait_until |= (1 << 15) | (1 << 17) | (1 << 18); - break; - default: - return; - } - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH(wait_until); - END_BATCH(); - } + BATCH_LOCALS(&rmesa->radeon); + uint32_t wait_until; + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags)); + END_BATCH(); + } else { + switch(flags) { + case R300_WAIT_2D: + wait_until = (1 << 14); + break; + case R300_WAIT_3D: + wait_until = (1 << 15); + break; + case R300_NEW_WAIT_2D_3D: + wait_until = (1 << 14) | (1 << 15); + break; + case R300_NEW_WAIT_2D_2D_CLEAN: + wait_until = (1 << 14) | (1 << 16) | (1 << 18); + break; + case R300_NEW_WAIT_3D_3D_CLEAN: + wait_until = (1 << 15) | (1 << 17) | (1 << 18); + break; + case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: + wait_until = (1 << 14) | (1 << 16) | (1 << 18); + wait_until |= (1 << 15) | (1 << 17) | (1 << 18); + break; + default: + return; + } + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); + OUT_BATCH(wait_until); + END_BATCH(); + } } extern int r300EmitArrays(GLcontext * ctx); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 63989636c2f..02c4b1cb408 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -70,7 +70,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, struct radeon_renderbuffer *rrb, struct radeon_renderbuffer *rrbd) { - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); GLcontext *ctx = r300->radeon.glCtx; __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; GLuint cbpitch = 0; @@ -205,7 +205,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, static void r300EmitClearState(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; int i; int has_tcl = 1; diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index cb6652fabef..c81393e7476 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -189,44 +189,44 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) { - BATCH_LOCALS(rmesa); - - if (vertex_count > 0) { - BEGIN_BATCH(8); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | - ((vertex_count + 0) << 16) | - type | - R300_VAP_VF_CNTL__INDEX_SIZE_32bit); - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); - OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); - OUT_BATCH_RELOC(rmesa->state.elt_dma_offset, - rmesa->state.elt_dma_bo, - rmesa->state.elt_dma_offset, - RADEON_GEM_DOMAIN_GTT, 0, 0); - OUT_BATCH(vertex_count); - } else { - OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); - OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); - OUT_BATCH(rmesa->state.elt_dma_offset); - OUT_BATCH(vertex_count); - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.elt_dma_bo, - RADEON_GEM_DOMAIN_GTT, 0, 0); - } - END_BATCH(); - } + BATCH_LOCALS(&rmesa->radeon); + + if (vertex_count > 0) { + BEGIN_BATCH(8); + OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); + OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | + ((vertex_count + 0) << 16) | + type | + R300_VAP_VF_CNTL__INDEX_SIZE_32bit); + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); + OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); + OUT_BATCH_RELOC(rmesa->state.elt_dma_offset, + rmesa->state.elt_dma_bo, + rmesa->state.elt_dma_offset, + RADEON_GEM_DOMAIN_GTT, 0, 0); + OUT_BATCH(vertex_count); + } else { + OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); + OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); + OUT_BATCH(rmesa->state.elt_dma_offset); + OUT_BATCH(vertex_count); + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->state.elt_dma_bo, + RADEON_GEM_DOMAIN_GTT, 0, 0); + } + END_BATCH(); + } } static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) { - BATCH_LOCALS(rmesa); - uint32_t voffset; + BATCH_LOCALS(&rmesa->radeon); + uint32_t voffset; int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; int i; - + if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, offset); @@ -236,91 +236,91 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH(nr); - if (!rmesa->radeon.radeonScreen->kernel_mm) { - for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->state.aos[i].components << 0) | - (rmesa->state.aos[i].stride << 8) | - (rmesa->state.aos[i + 1].components << 16) | - (rmesa->state.aos[i + 1].stride << 24)); - - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; - OUT_BATCH_RELOC(voffset, - rmesa->state.aos[i].bo, - voffset, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; - OUT_BATCH_RELOC(voffset, - rmesa->state.aos[i+1].bo, - voffset, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - - if (nr & 1) { - OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | - (rmesa->state.aos[nr - 1].stride << 8)); - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; - OUT_BATCH_RELOC(voffset, - rmesa->state.aos[nr - 1].bo, - voffset, + if (!rmesa->radeon.radeonScreen->kernel_mm) { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->state.aos[i].components << 0) | + (rmesa->state.aos[i].stride << 8) | + (rmesa->state.aos[i + 1].components << 16) | + (rmesa->state.aos[i + 1].stride << 24)); + + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[i].bo, + voffset, RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - } else { - for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->state.aos[i].components << 0) | - (rmesa->state.aos[i].stride << 8) | - (rmesa->state.aos[i + 1].components << 16) | - (rmesa->state.aos[i + 1].stride << 24)); - - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; - OUT_BATCH(voffset); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; - OUT_BATCH(voffset); - } - - if (nr & 1) { - OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | + 0, 0); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[i+1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + + if (nr & 1) { + OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | + (rmesa->state.aos[nr - 1].stride << 8)); + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[nr - 1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + } else { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->state.aos[i].components << 0) | + (rmesa->state.aos[i].stride << 8) | + (rmesa->state.aos[i + 1].components << 16) | + (rmesa->state.aos[i + 1].stride << 24)); + + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; + OUT_BATCH(voffset); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; + OUT_BATCH(voffset); + } + + if (nr & 1) { + OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | (rmesa->state.aos[nr - 1].stride << 8)); - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; - OUT_BATCH(voffset); - } - for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[i+0].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[i+1].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - if (nr & 1) { - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[nr-1].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH(voffset); + } + for (i = 0; i + 1 < nr; i += 2) { + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->state.aos[i+0].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->state.aos[i+1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + if (nr & 1) { + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->state.aos[nr-1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } } - } END_BATCH(); } static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); BEGIN_BATCH(3); OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); @@ -331,7 +331,7 @@ static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, int start, int end, int prim) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); int type, num_verts; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 0108f7cf6af..03fc2107dba 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -636,7 +636,7 @@ void r300DestroySwtcl(GLcontext *ctx) void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n", @@ -652,7 +652,7 @@ void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_b void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); int type, num_verts; type = r300PrimitiveType(rmesa, primitive); diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index 018049b4523..fbcbf72b2bf 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -31,7 +31,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, /** * Same as BEGIN_BATCH, but do not cause automatic state emits. */ -#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_r300, n, 0, __FILE__, __FUNCTION__, __LINE__) +#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, 0, __FILE__, __FUNCTION__, __LINE__) /** * Write one dword to the command buffer. @@ -89,5 +89,17 @@ void rcommonBeginBatch(radeonContextPtr rmesa, } while(0) +/** Single register write to command buffer; requires 2 dwords. */ +#define OUT_BATCH_REGVAL(reg, val) \ + OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \ + OUT_BATCH((val)) +/** Continuous register range write to command buffer; requires 1 dword, + * expects count dwords afterwards for register contents. */ +#define OUT_BATCH_REGSEQ(reg, count) \ + OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count))); + +/** Write a 32 bit float to the ring; requires 1 dword. */ +#define OUT_BATCH_FLOAT32(f) \ + OUT_BATCH(radeonPackFloat32((f))); #endif diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 2748c51a59c..d6e15bc3b86 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -343,6 +343,51 @@ struct radeon_context { #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) +/** + * This function takes a float and packs it into a uint32_t + */ +static INLINE uint32_t radeonPackFloat32(float fl) +{ + union { + float fl; + uint32_t u; + } u; + + u.fl = fl; + return u.u; +} + +/* This is probably wrong for some values, I need to test this + * some more. Range checking would be a good idea also.. + * + * But it works for most things. I'll fix it later if someone + * else with a better clue doesn't + */ +static INLINE uint32_t radeonPackFloat24(float f) +{ + float mantissa; + int exponent; + uint32_t float24 = 0; + + if (f == 0.0) + return 0; + + mantissa = frexpf(f, &exponent); + + /* Handle -ve */ + if (mantissa < 0) { + float24 |= (1 << 23); + mantissa = mantissa * -1.0; + } + /* Handle exponent, bias of 63 */ + exponent += 62; + float24 |= (exponent << 16); + /* Kill 7 LSB of mantissa */ + float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7; + + return float24; +} + /* ================================================================ * Debugging: */ -- 2.30.2