From 08d9ade8a79e68865afafbed9b81cd81c49acb1f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 29 May 2020 13:35:40 +0100 Subject: [PATCH] write-release moves out of "ALU valid" due to using alu_pulse --- src/soc/experiment/compalu_multi.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 9810f3e0..e2a62f8a 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -271,6 +271,10 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): bro = Repl(self.busy_o, self.n_src) m.d.comb += self.rd.rel.eq(src_l.q & bro & slg) # src1/src2 req rel + # write-release gated by busy and by shadow + brd = Repl(self.busy_o & self.shadown_i, self.n_dst) + m.d.comb += self.wr.rel.eq(req_l.q & brd) + # on a go_read, tell the ALU we're accepting data. # NOTE: this spells TROUBLE if the ALU isn't ready! # go_read is only valid for one clock! @@ -281,8 +285,6 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): brd = Repl(self.busy_o & self.shadown_i, self.n_dst) # only proceed if ALU says its output is valid with m.If(self.alu.n.valid_o): - # when ALU ready, write req release out. waits for shadow - m.d.comb += self.wr.rel.eq(req_l.q & brd) # when output latch is ready, and ALU says ready, accept ALU output with m.If(reset): m.d.comb += self.alu.n.ready_i.eq(1) # tells ALU "got it" -- 2.30.2