From 08e0b15e025be49376241fd5c3e623bc063693c4 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sun, 7 Jun 2020 17:47:10 -0300 Subject: [PATCH] Assign the one-clock delay operation from ADD to SHR This keeps the ADD delay as it was, originally. --- src/soc/experiment/alu_hier.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index 0301d744..8be6533f 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -259,12 +259,12 @@ class ALU(Elaboratable): # MUL, to take 5 instructions with m.If(self.op.insn_type == InternalOp.OP_MUL_L64): m.d.sync += self.counter.eq(5) - # SHIFT to take 7 + # SHIFT to take 1, straight away with m.Elif(self.op.insn_type == InternalOp.OP_SHR): - m.d.sync += self.counter.eq(7) - # ADD/SUB to take 1, straight away - with m.Elif(self.op.insn_type == InternalOp.OP_ADD): m.d.sync += self.counter.eq(1) + # ADD/SUB to take 3 + with m.Elif(self.op.insn_type == InternalOp.OP_ADD): + m.d.sync += self.counter.eq(3) # others to take no delay with m.Else(): m.d.comb += go_now.eq(1) @@ -461,6 +461,10 @@ def alu_sim(dut): print ("alu_sim sub", result) assert (result == 2) + result = yield from run_op(dut, 13, 2, InternalOp.OP_SHR) + print ("alu_sim shr", result) + assert (result == 3) + def test_alu(): alu = ALU(width=16) -- 2.30.2