From 08e8006e0f7f7924099763138e86940ba3eb5cd6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 19 Dec 2020 15:32:59 +0000 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index 087d05e6c..197253748 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -11,9 +11,9 @@ Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]] # Format | 0.5|6.10|11.15|16.20| 21..24..25 | 26...30 |31| name | -|----|----|-----|-----|-------------|---------|--|---------| +| -- | -- | --- | --- | ----------- | ------- |--| ------- | | 19 | RT | RA | | XO[0:4] | XO[5:9] |Rc| XL-Form | -| 19 | RT | RA |imm | i // vs ms | NNNNN |Rc| setvl | +| 19 | RT | RA | imm | i // vs ms | NNNNN |Rc| setvl | Note that imm spans 7 bits (16 to 22), and that bit 22 is reserved and must be zero. Setting bit 22 causes an illegal exception. -- 2.30.2