From 09073d71224ae99287a8bae12599fda2e3478383 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 7 May 2022 14:54:33 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 3ef9c84f7..4d15dee41 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -742,10 +742,9 @@ much easier for the main CPU to take over in the event that PEs are currently occupied. Plus, the twin lessons that inventing ISAs, even a small one, is hard (mostly in compiler writing) and how complex GPU Task Scheduling is, are being heard loud and clear. -Put another way: -* if the PEs run a foriegn ISA, then the Basic Blocks embedded inside - the ZOLC Loops must be in that ISA **OR** +Put another way: if the PEs run a foriegn ISA, then the Basic Blocks embedded inside the ZOLC Loops must be in that ISA and therefore: + * In order that the main CPU can execute the same sequence if necessary, the CPU must support dual ISAs: Power and PE **OR** * There must be a JIT binary-translator which either turns PE code -- 2.30.2