From 092d2d78fa19a5c73863cb89c5d680cbd2afe027 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 15 Mar 2019 09:33:44 +0000 Subject: [PATCH] update comments --- src/add/example_buf_pipe.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py index 40224b47..2604262c 100644 --- a/src/add/example_buf_pipe.py +++ b/src/add/example_buf_pipe.py @@ -70,7 +70,7 @@ class ExampleStage: def __init__(self): """ i_data can be a DIFFERENT type from everything else o_data, r_data and result are best of the same type. - however this is not strictly the case. an intermediate + however this is not strictly necessary. an intermediate transformation process could hypothetically be applied, however it is result and r_data that definitively need to be of the same (intermediary) type, as it is both result and r_data that @@ -93,7 +93,9 @@ class ExampleStage: return self.result.eq(self.i_data + 1) def update_buffer(self): - """ copies the result into the intermediate register r_data + """ copies the result into the intermediate register r_data, + which will need to be outputted on a subsequent cycle + prior to allowing "normal" operation. """ return self.r_data.eq(self.result) -- 2.30.2