From 0949e113f0979adb56e1e8af4106d39bfd56b55f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 21 Jul 2020 10:41:36 +0100 Subject: [PATCH] correct trap spec page interrupt ref --- src/soc/fu/trap/main_stage.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 39f4326d..37ea4af2 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -150,7 +150,7 @@ class TrapMainStage(PipeModBase): # generate trap-type program interrupt self.trap(m, trapaddr<<4, cia_i) with m.If(traptype == 0): - # say trap occurred (see 3.0B Book III 7.5.9) + # say trap occurred (see 3.0B Book III 6.5.9 p1074-6) comb += srr1_o.data[PI.TRAP].eq(1) with m.If(traptype & TT.PRIV): comb += srr1_o.data[PI.PRIV].eq(1) -- 2.30.2