From 096e95cb59a213a04e3f10718d362533f746d5e4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 1 Mar 2015 16:56:48 +0100 Subject: [PATCH] uart: use data instead of d on endpoint's layouts (coherency with others cores) --- misoclib/com/uart/__init__.py | 4 ++-- misoclib/com/uart/phy/serial.py | 8 ++++---- misoclib/com/uart/phy/sim.py | 8 ++++---- misoclib/tools/litescope/bridge/uart2wb.py | 14 +++++++------- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/misoclib/com/uart/__init__.py b/misoclib/com/uart/__init__.py index 44a74e06..32154723 100644 --- a/misoclib/com/uart/__init__.py +++ b/misoclib/com/uart/__init__.py @@ -16,12 +16,12 @@ class UART(Module, AutoCSR): self.sync += [ If(self._rxtx.re, phy.tx.sink.stb.eq(1), - phy.tx.sink.d.eq(self._rxtx.r), + phy.tx.sink.data.eq(self._rxtx.r), ).Elif(phy.tx.sink.ack, phy.tx.sink.stb.eq(0) ), If(phy.rx.source.stb, - self._rxtx.w.eq(phy.rx.source.d) + self._rxtx.w.eq(phy.rx.source.data) ) ] self.comb += [ diff --git a/misoclib/com/uart/phy/serial.py b/misoclib/com/uart/phy/serial.py index 35f5b7d8..8ca91b8e 100644 --- a/misoclib/com/uart/phy/serial.py +++ b/misoclib/com/uart/phy/serial.py @@ -5,7 +5,7 @@ from migen.flow.actor import Sink, Source class UARTPHYSerialRX(Module): def __init__(self, pads, tuning_word): - self.source = Source([("d", 8)]) + self.source = Source([("data", 8)]) ### uart_clk_rxen = Signal() phase_accumulator_rx = Signal(32) @@ -17,7 +17,7 @@ class UARTPHYSerialRX(Module): rx_bitcount = Signal(4) rx_busy = Signal() rx_done = self.source.stb - rx_data = self.source.d + rx_data = self.source.data self.sync += [ rx_done.eq(0), rx_r.eq(rx), @@ -54,7 +54,7 @@ class UARTPHYSerialRX(Module): class UARTPHYSerialTX(Module): def __init__(self, pads, tuning_word): - self.sink = Sink([("d", 8)]) + self.sink = Sink([("data", 8)]) ### uart_clk_txen = Signal() phase_accumulator_tx = Signal(32) @@ -67,7 +67,7 @@ class UARTPHYSerialTX(Module): self.sync += [ self.sink.ack.eq(0), If(self.sink.stb & ~tx_busy & ~self.sink.ack, - tx_reg.eq(self.sink.d), + tx_reg.eq(self.sink.data), tx_bitcount.eq(0), tx_busy.eq(1), pads.tx.eq(0) diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py index 177b97ca..a0f47b37 100644 --- a/misoclib/com/uart/phy/sim.py +++ b/misoclib/com/uart/phy/sim.py @@ -5,14 +5,14 @@ class UARTPHYSim(Module): def __init__(self, pads): self.dw = 8 self.tuning_word = Signal(32) - self.sink = Sink([("d", 8)]) - self.source = Source([("d", 8)]) + self.sink = Sink([("data", 8)]) + self.source = Source([("data", 8)]) self.comb += [ pads.source_stb.eq(self.sink.stb), - pads.source_d.eq(self.sink.d), + pads.source_data.eq(self.sink.data), self.sink.ack.eq(pads.source_ack), self.source.stb.eq(pads.sink_stb), - self.source.d.eq(pads.sink_d) + self.source.data.eq(pads.sink_data) ] diff --git a/misoclib/tools/litescope/bridge/uart2wb.py b/misoclib/tools/litescope/bridge/uart2wb.py index b8a3c4f1..2b17d742 100644 --- a/misoclib/tools/litescope/bridge/uart2wb.py +++ b/misoclib/tools/litescope/bridge/uart2wb.py @@ -80,11 +80,11 @@ class LiteScopeUART2WB(Module, AutoCSR): tx_data_ce = Signal() self.sync += [ - If(cmd_ce, cmd.eq(uart.source.d)), - If(length_ce, length.eq(uart.source.d)), - If(address_ce, address.eq(Cat(uart.source.d, address[0:24]))), + If(cmd_ce, cmd.eq(uart.source.data)), + If(length_ce, length.eq(uart.source.data)), + If(address_ce, address.eq(Cat(uart.source.data, address[0:24]))), If(rx_data_ce, - data.eq(Cat(uart.source.d, data[0:24])) + data.eq(Cat(uart.source.data, data[0:24])) ).Elif(tx_data_ce, data.eq(self.wishbone.dat_r) ) @@ -102,8 +102,8 @@ class LiteScopeUART2WB(Module, AutoCSR): timeout.reset.eq(1), If(uart.source.stb, cmd_ce.eq(1), - If( (uart.source.d == self.cmds["write"]) | - (uart.source.d == self.cmds["read"]), + If( (uart.source.data == self.cmds["write"]) | + (uart.source.data == self.cmds["read"]), NextState("RECEIVE_LENGTH") ), byte_counter.reset.eq(1), @@ -168,7 +168,7 @@ class LiteScopeUART2WB(Module, AutoCSR): ) ) self.comb += \ - chooser(data, byte_counter.value, uart.sink.d, n=4, reverse=True) + chooser(data, byte_counter.value, uart.sink.data, n=4, reverse=True) fsm.act("SEND_DATA", uart.sink.stb.eq(1), If(uart.sink.ack, -- 2.30.2