From 098079a9ea32ca293a9a1eedaadc5ee280bcc40f Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 9 Jun 2023 19:28:40 +0100 Subject: [PATCH] --- openpower/sv/po9_encoding/discussion.mdwn | 63 ++++++++++++++++------- 1 file changed, 44 insertions(+), 19 deletions(-) diff --git a/openpower/sv/po9_encoding/discussion.mdwn b/openpower/sv/po9_encoding/discussion.mdwn index d3f1d8df6..829888f91 100644 --- a/openpower/sv/po9_encoding/discussion.mdwn +++ b/openpower/sv/po9_encoding/discussion.mdwn @@ -11,7 +11,7 @@ a specific view to attaining high-speed massive-wide multi-issue decode is a high priority. therefore especially length-detection must be kept brutally simple. -# alternative 32-64 encoding (1) **superseded** +# **superseded** alternative 32-64 encoding (1) conflict to resolve: EXT90x and EXT232. they are indistinguishable. @@ -60,7 +60,7 @@ Instruction allocation restrictions: * but those types of space-saving instructions **also need to be Vectorizable* -# alternative 32-64 encoding (2) **superseded** +# **superseded** alternative 32-64 encoding (2) requires reducing SVP64Single to 23 bits. luckily there are 2 spare @@ -106,27 +106,48 @@ Length detection: aim of this idea is to attempt simplification of area identification and length. the 55-bit area is eliminated and may only be reintroduced -by sacrificing parts of EXT200-231, bear in mind that EXT209 is already +by sacrificing parts of EXT200-231, bear in mind that EXT240 is already unavailable (used by EXT900). - ``` -|0-5| 6-29 |30 31|32|33-36|37 | 38-61 | 62-63 | Description | -|---|--------|-----|--|-----|---|-------|-------|------------------| +|0-5| 6-29 |30 31|32 |33-37 | 38-61 | 62-63 | Description | +|---|--------|-----|---|--------|-------|-------|------------------| |PO9| xxxx | 0 0 | (next new instruction) | 32-bit EXT900 | -|PO9| 0000 | 1 0 | 0 1000 1 | xxxx | 00 | RESERVED | -|PO9| !ZERO | 1 0 | 0 1000 1 | xxxx | 00 | SSingle:EXT900 | -|PO9| nnnn | 1 0 | 0 1000 1 | xxxx | 01 | SVP64:EXT900 | -|PO9| xxxx | 1 0 | 0 1000 1 | xxxx | 10 | RESERVED | -|PO9| xxxx | 1 0 | 0 1000 1 | xxxx | 11 | RESERVED | -|PO9| !ZERO | 1 0 | 0 | !PO9 | xxxx | SSingle:EXT200-231 | -|PO9| 0000 | 1 0 | 0 | !PO9 | xxxx | Scalar EXT200-231 | -|PO9| nnnn | 1 0 | 1 | !PO9 | xxxx | SVP64:EXT200-231 | -|PO9| 0000 | 0 1 | Defined Word-instruction | 32-bit Unvec in 64b| -|PO9| !ZERO | 0 1 | Defined Word-instruction | SSingle:EXT000-063 | -|PO9| nnnn | 1 1 | Defined Word-instruction | SVP64:EXT000-063 | +|PO9| 0000 | 1 0 | 0 | 10001 | //// | 00 | RESERVED | +|PO9| !ZERO | 1 0 | 0 | 10001 | xxxx | 00 | SSingle:EXT900 | +|PO9| SVRM | 1 0 | 0 | 10001 | xxxx | 01 | SVP64:EXT900 | +|PO9| //// | 1 0 | 0 | 10001 | //// | 10 | RESERVED | +|PO9| //// | 1 0 | 0 | 10001 | //// | 11 | RESERVED | +|PO9| !ZERO | 1 0 | 0 | !PO9 | xxxx | SSingle:EXT232-263 | +|PO9| 0000 | 1 0 | 0 | !PO9 | xxxx | Scalar EXT232-263 | +|PO9| SVRM | 1 0 | 1 | !PO9 | xxxx | SVP64:EXT232-263 | +|PO9| 0000 | 0 1 | Defined Word-instruction | 32-bit Unvec in 64b| +|PO9| !ZERO | 0 1 | Defined Word-instruction | SSingle:EXT000-063 | +|PO9| SVRM | 1 1 | Defined Word-instruction | SVP64:EXT000-063 | ``` +**Notes**: + +* with `setvl` `svindex` `svshape` and `svshape2` being Unvectorizable Management +instructions requiring 6-bit `XO` and needing EXT1xx variants later, they are +best placed in EXT0xx. EXT900 is Vectorizable and extremely precious. Further +complication of Decode to create Vectorized EXT900 and Unvectorized EXT901 +is inadviseable (rejected in alternative 1) +* EXT200-231 is intended to be partially-filled with LD/ST-Immediate-Postincrement + and it is strongly recommended that the exact same Primary Opcode be + used, matching the lower 5 bits. `lzbu` is EXT033, therefore `lzbup` is + recommended to be EXT233. This will greatly simplify Decode. +* With no "overlapping" Encodings permitted on top of EXT232-263 (except + EXT240) Speculative Decode may begin early in Multi-Issue systems safe + that for the most part the 32-bit instruction is either going to be + EXT0xx or EXT2xx, regardless of whether it is SVP64-Prefixed. + LD/ST-Immediate-Postincrement discernment from + LD/ST-Immediate is delayed, but Decode of other EXT232-263 operations + are *also delayed* pending identification. + + +**Identification**: + The following identification-criteria may be easily verified by taking a copy of the table above and striking out each line that fails each test. Only EXT000-063 is not by a "process of elimination" (if ... return True) @@ -140,13 +161,17 @@ test. Only EXT000-063 is not by a "process of elimination" (if ... return True) else return 64 ``` -**EXT200-231:** +**EXT232-263:** ``` if not PO9 return False + # eliminate EXT900 if Word[30:31] == 0b00 return False + # eliminate EXT0xx + if Word[31] == 0b1 return False + # eliminate EXT900 and reserved areas if Word[33:37] != 0b10001 return False - # if Word[33:37] != XXXXX return False # 50-bit + # return True ``` -- 2.30.2