From 098a1cb5cd2af15504c122f8a722194adda29899 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 16 Jun 2023 17:52:07 -0700 Subject: [PATCH] remove Rc=1 from fmvfg[s] --- openpower/isa/fpmove.mdwn | 10 ++++------ openpower/isatables/RM-2P-1S1D.csv | 4 ++-- openpower/isatables/minor_59.csv | 2 +- openpower/isatables/minor_63.csv | 2 +- src/openpower/sv/sv_analysis.py | 3 +++ src/openpower/test/fmv_fcvt/fmv_fcvt.py | 2 +- 6 files changed, 12 insertions(+), 11 deletions(-) diff --git a/openpower/isa/fpmove.mdwn b/openpower/isa/fpmove.mdwn index 179119cf..09b55c53 100644 --- a/openpower/isa/fpmove.mdwn +++ b/openpower/isa/fpmove.mdwn @@ -111,8 +111,7 @@ Special Registers Altered: X-Form -* fmvfg FRT,RB (Rc=0) -* fmvfg. FRT,RB (Rc=1) +* fmvfg FRT,RB Pseudo-code: @@ -120,14 +119,13 @@ Pseudo-code: Special Registers Altered: - CR1 (if Rc=1) + None # [DRAFT] Floating Move From GPR Single X-Form -* fmvfgs FRT,RB (Rc=0) -* fmvfgs. FRT,RB (Rc=1) +* fmvfgs FRT,RB Pseudo-code: @@ -135,4 +133,4 @@ Pseudo-code: Special Registers Altered: - CR1 (if Rc=1) + None diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv index 58859975..0d4c25f8 100644 --- a/openpower/isatables/RM-2P-1S1D.csv +++ b/openpower/isatables/RM-2P-1S1D.csv @@ -15,6 +15,8 @@ mfspr,NORMAL,,2P,EXTRA3,EN,d:RS,s:SPR,0,0,SPR,0,0,RT,0,0,0 popcntw,NORMAL,,2P,EXTRA3,EN,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0 mtspr,NORMAL,,2P,EXTRA3,EN,d:SPR,s:RS,0,0,RS,0,0,SPR,0,0,0 popcntd,NORMAL,,2P,EXTRA3,EN,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0 +fmvfgs,NORMAL,,2P,EXTRA3,EN,d:FRT,s:RB,0,0,0,RB,0,FRT,0,0,0 +fmvfg,NORMAL,,2P,EXTRA3,EN,d:FRT,s:RB,0,0,0,RB,0,FRT,0,0,0 addic,NORMAL,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0 addi,NORMAL,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 addis,NORMAL,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 @@ -73,7 +75,6 @@ fcfids,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fexp2s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 flog2s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fmvtgs,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0 -fmvfgs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:RB,0,0,0,RB,0,FRT,0,CR1,0 fexps,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 flogs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fexp10s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 @@ -132,7 +133,6 @@ flog10p1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fexp2,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 flog2,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fmvtg,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0 -fmvfg,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:RB,0,0,0,RB,0,FRT,0,CR1,0 fexp,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 flog,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 29/14=fctidu,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv index 06e5e948..5dd238c8 100644 --- a/openpower/isatables/minor_59.csv +++ b/openpower/isatables/minor_59.csv @@ -82,4 +82,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 1111001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fremainders,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1110001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvtgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fcvtfgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1110001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvfgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1110001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fmvfgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/openpower/isatables/minor_63.csv b/openpower/isatables/minor_63.csv index 2bd25b8a..c5d8a4c6 100644 --- a/openpower/isatables/minor_63.csv +++ b/openpower/isatables/minor_63.csv @@ -109,4 +109,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 1100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fcvttgo,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1110001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvtg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fcvtfg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1110001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvfg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1110001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fmvfg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index 595a6cc8..f9a74a58 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -525,6 +525,9 @@ def extra_classifier(insn_name, value, name, res, regs): elif regs == ['', 'RB', '', 'FRT', '', 'CR1']: res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3 res['1'] = 's:RB' # RB: Rsrc1_EXTRA3 + elif regs == ['', 'RB', '', 'FRT', '', '']: + res['0'] = 'd:FRT' # FRT: Rdest1_EXTRA3 + res['1'] = 's:RB' # RB: Rsrc1_EXTRA3 elif regs == ['', 'FRB', '', 'RT', '', 'CR0']: res['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA3 res['1'] = 's:FRB' # FRB: Rsrc1_EXTRA3 diff --git a/src/openpower/test/fmv_fcvt/fmv_fcvt.py b/src/openpower/test/fmv_fcvt/fmv_fcvt.py index 108ca0e0..53909edb 100644 --- a/src/openpower/test/fmv_fcvt/fmv_fcvt.py +++ b/src/openpower/test/fmv_fcvt/fmv_fcvt.py @@ -603,7 +603,7 @@ class FMvFCvtCases(TestAccumulatorBase): s = "s" if bfp32 else "" rc_str = "." if Rc else "" tg_p = _cached_program(f"fmvtg{s}{rc_str} 3, 0") - # fmvfg[s]. shouldn't exist since Rc=1 is basically useless due to + # fmvfg[s]. doesn't exist since Rc=1 is basically useless due to # fmv* not changing any FPSCR bits fg_p = _cached_program(f"fmvfg{s} 0, 3") tg_gprs = [0] * 32 -- 2.30.2