From 0998547c269af1f9bd116538f1cea6641e56608d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 16 Apr 2018 19:09:57 +0100 Subject: [PATCH] add SIMD comparison section --- simple_v_extension.mdwn | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 5b5ef6692..94ee77af7 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1193,9 +1193,10 @@ the question is asked "How can each of the proposals effectively implement a SIMD architecture where the ALU becomes responsible for the parallelism, Alt-RVP ALUs would likewise be so responsible... with *additional* (lane-based) parallelism on top. -* Thus at least some of the downsides of SIMD are avoided (architectural - upgrades introducing 128-bit then 256-bit then 512-bit variants of the - exact same 64-bit SIMD block) +* Thus at least some of the downsides of SIMD ISA O(N^3) proliferation by + at least one dimension are avoided (architectural upgrades introducing + 128-bit then 256-bit then 512-bit variants of the exact same 64-bit + SIMD block) * Thus, unfortunately, Alt-RVP would suffer the same inherent proliferation of instructions as SIMD, albeit not quite as badly (due to Lanes). * In the same discussion for Alt-RVP, an additional proposal was made to -- 2.30.2