From 09c26c55bb4357f0b7204d8a78806aa7ad12068f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Sep 2019 17:22:02 -0700
Subject: [PATCH] Get rid of sigBset too

---
 passes/pmgen/xilinx_dsp.cc  |  4 ----
 passes/pmgen/xilinx_dsp.pmg | 18 ++++++++++--------
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 0d1937844..c742ef84d 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -23,10 +23,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-template<class T> inline bool includes(const T &lhs, const T &rhs) {
-	return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
-}
-#include <set>
 #include "passes/pmgen/xilinx_dsp_pm.h"
 
 void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 598276063..d37792b29 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -1,24 +1,25 @@
 pattern xilinx_dsp
 
 state <SigBit> clock
-state <std::set<SigBit>> sigBset
-state <SigSpec> sigA sigC sigM sigP sigPused
+state <SigSpec> sigA sigB sigC sigM sigP sigPused
 state <IdString> ffMmuxAB postAddAB postAddMuxAB
 
 match dsp
 	select dsp->type.in(\DSP48E1)
 endmatch
 
-code sigA sigBset
+code sigA sigB
 	sigA = port(dsp, \A);
 	int i;
 	for (i = GetSize(sigA)-1; i > 0; i--)
 		if (sigA[i] != sigA[i-1])
 			break;
 	sigA.remove(i, GetSize(sigA)-i);
-	SigSpec B = port(dsp, \B);
-	B.remove_const();
-	sigBset = B.to_sigbit_set();
+	sigB = port(dsp, \B);
+	for (i = GetSize(sigB)-1; i > 0; i--)
+		if (sigB[i] != sigB[i-1])
+			break;
+	sigB.remove(i, GetSize(sigB)-i);
 endcode
 
 code sigM
@@ -58,11 +59,12 @@ endcode
 
 match ffB
 	if param(dsp, \BREG).as_int() == 0
-	if !sigBset.empty()
 	select ffB->type.in($dff)
 	// DSP48E1 does not support clock inversion
 	select param(ffB, \CLK_POLARITY).as_bool()
-	filter includes(port(ffB, \Q).to_sigbit_set(), sigBset)
+	filter GetSize(port(ffB, \Q)) >= GetSize(sigB)
+	slice offset GetSize(port(ffB, \Q))
+	filter offset+GetSize(sigB) <= GetSize(port(ffB, \Q)) && port(ffB, \Q).extract(offset, GetSize(sigB)) == sigB
 	optional
 endmatch
 
-- 
2.30.2